Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24165812	21159	0	0
attest_sw_binding_0_rd_A	24165812	2213	0	0
attest_sw_binding_1_rd_A	24165812	2289	0	0
attest_sw_binding_2_rd_A	24165812	2384	0	0
attest_sw_binding_3_rd_A	24165812	2376	0	0
attest_sw_binding_4_rd_A	24165812	2368	0	0
attest_sw_binding_5_rd_A	24165812	2252	0	0
attest_sw_binding_6_rd_A	24165812	2433	0	0
attest_sw_binding_7_rd_A	24165812	2270	0	0
intr_enable_rd_A	24165812	2817	0	0
key_version_rd_A	24165812	2130	0	0
max_creator_key_ver_regwen_rd_A	24165812	2373	0	0
max_owner_int_key_ver_regwen_rd_A	24165812	2222	0	0
max_owner_key_ver_regwen_rd_A	24165812	2330	0	0
reseed_interval_regwen_rd_A	24165812	2248	0	0
salt_0_rd_A	24165812	2266	0	0
salt_1_rd_A	24165812	2212	0	0
salt_2_rd_A	24165812	2323	0	0
salt_3_rd_A	24165812	2140	0	0
salt_4_rd_A	24165812	2316	0	0
salt_5_rd_A	24165812	2280	0	0
salt_6_rd_A	24165812	2166	0	0
salt_7_rd_A	24165812	2195	0	0
sealing_sw_binding_0_rd_A	24165812	2146	0	0
sealing_sw_binding_1_rd_A	24165812	2216	0	0
sealing_sw_binding_2_rd_A	24165812	2229	0	0
sealing_sw_binding_3_rd_A	24165812	2265	0	0
sealing_sw_binding_4_rd_A	24165812	2254	0	0
sealing_sw_binding_5_rd_A	24165812	2332	0	0
sealing_sw_binding_6_rd_A	24165812	2239	0	0
sealing_sw_binding_7_rd_A	24165812	2203	0	0
sideload_clear_rd_A	24165812	2247	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	21159	0	0
T5	0	556	0	0
T12	27759	191	0	0
T13	32268	531	0	0
T14	2847	0	0	0
T15	85574	317	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T51	0	516	0	0
T56	0	459	0	0
T59	0	91	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	60	0	0
T117	0	772	0	0
T118	0	527	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2213	0	0
T12	27759	31	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	25	0	0
T130	0	39	0	0
T133	0	4	0	0
T144	0	77	0	0
T158	0	35	0	0
T170	0	8	0	0
T171	0	22	0	0
T172	0	259	0	0
T173	0	1	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2289	0	0
T12	27759	21	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	26	0	0
T130	0	62	0	0
T133	0	2	0	0
T144	0	91	0	0
T158	0	43	0	0
T170	0	33	0	0
T171	0	15	0	0
T172	0	270	0	0
T173	0	4	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2384	0	0
T12	27759	43	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T109	0	218	0	0
T116	0	23	0	0
T130	0	32	0	0
T133	0	2	0	0
T144	0	90	0	0
T158	0	33	0	0
T170	0	45	0	0
T171	0	26	0	0
T172	0	237	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2376	0	0
T12	27759	18	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	46	0	0
T130	0	38	0	0
T133	0	9	0	0
T144	0	91	0	0
T158	0	62	0	0
T170	0	39	0	0
T171	0	8	0	0
T172	0	249	0	0
T173	0	10	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2368	0	0
T12	27759	23	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	44	0	0
T130	0	46	0	0
T133	0	1	0	0
T144	0	79	0	0
T158	0	48	0	0
T170	0	26	0	0
T171	0	31	0	0
T172	0	241	0	0
T173	0	1	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2252	0	0
T12	27759	27	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	34	0	0
T130	0	30	0	0
T133	0	3	0	0
T144	0	82	0	0
T158	0	35	0	0
T170	0	22	0	0
T171	0	32	0	0
T172	0	255	0	0
T173	0	21	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2433	0	0
T12	27759	16	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	28	0	0
T130	0	7	0	0
T133	0	2	0	0
T144	0	74	0	0
T158	0	35	0	0
T170	0	33	0	0
T171	0	52	0	0
T172	0	306	0	0
T173	0	6	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2270	0	0
T12	27759	47	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	32	0	0
T130	0	50	0	0
T133	0	3	0	0
T144	0	86	0	0
T158	0	48	0	0
T170	0	36	0	0
T171	0	37	0	0
T172	0	257	0	0
T173	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2817	0	0
T12	27759	39	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T54	0	20	0	0
T60	0	19	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	16	0	0
T174	0	30	0	0
T175	0	51	0	0
T176	0	30	0	0
T177	0	39	0	0
T178	0	32	0	0
T179	0	19	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2130	0	0
T12	27759	25	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	30	0	0
T130	0	42	0	0
T133	0	2	0	0
T144	0	82	0	0
T158	0	30	0	0
T170	0	21	0	0
T171	0	20	0	0
T172	0	256	0	0
T173	0	11	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2373	0	0
T12	27759	31	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	26	0	0
T130	0	20	0	0
T133	0	6	0	0
T144	0	106	0	0
T158	0	51	0	0
T170	0	10	0	0
T171	0	33	0	0
T172	0	281	0	0
T173	0	21	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2222	0	0
T12	27759	37	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	18	0	0
T130	0	37	0	0
T133	0	5	0	0
T144	0	66	0	0
T158	0	53	0	0
T170	0	44	0	0
T171	0	21	0	0
T172	0	214	0	0
T173	0	22	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2330	0	0
T12	27759	17	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T109	0	213	0	0
T116	0	29	0	0
T130	0	60	0	0
T133	0	3	0	0
T144	0	89	0	0
T158	0	47	0	0
T170	0	29	0	0
T171	0	28	0	0
T172	0	255	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2248	0	0
T12	27759	50	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	30	0	0
T130	0	74	0	0
T133	0	2	0	0
T144	0	50	0	0
T158	0	26	0	0
T170	0	19	0	0
T171	0	18	0	0
T172	0	260	0	0
T173	0	4	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2266	0	0
T12	27759	18	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	27	0	0
T130	0	59	0	0
T133	0	4	0	0
T144	0	84	0	0
T158	0	37	0	0
T170	0	49	0	0
T171	0	23	0	0
T172	0	235	0	0
T173	0	9	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2212	0	0
T12	27759	11	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T109	0	204	0	0
T116	0	32	0	0
T130	0	26	0	0
T133	0	4	0	0
T144	0	82	0	0
T158	0	34	0	0
T170	0	17	0	0
T171	0	32	0	0
T172	0	285	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2323	0	0
T12	27759	11	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	15	0	0
T130	0	39	0	0
T133	0	7	0	0
T144	0	75	0	0
T158	0	30	0	0
T170	0	32	0	0
T171	0	49	0	0
T172	0	217	0	0
T173	0	19	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2140	0	0
T12	27759	27	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	20	0	0
T130	0	36	0	0
T133	0	7	0	0
T144	0	73	0	0
T158	0	38	0	0
T170	0	28	0	0
T171	0	24	0	0
T172	0	205	0	0
T173	0	9	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2316	0	0
T12	27759	57	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T109	0	207	0	0
T116	0	27	0	0
T130	0	30	0	0
T144	0	80	0	0
T158	0	54	0	0
T170	0	34	0	0
T171	0	12	0	0
T172	0	264	0	0
T173	0	15	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2280	0	0
T12	27759	29	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	23	0	0
T130	0	9	0	0
T133	0	4	0	0
T144	0	77	0	0
T158	0	37	0	0
T170	0	25	0	0
T171	0	35	0	0
T172	0	274	0	0
T173	0	11	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2166	0	0
T12	27759	24	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	29	0	0
T130	0	15	0	0
T133	0	1	0	0
T144	0	76	0	0
T158	0	40	0	0
T170	0	15	0	0
T171	0	34	0	0
T172	0	252	0	0
T173	0	14	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2195	0	0
T12	27759	21	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T109	0	185	0	0
T116	0	30	0	0
T130	0	33	0	0
T133	0	4	0	0
T144	0	75	0	0
T158	0	39	0	0
T170	0	26	0	0
T171	0	28	0	0
T172	0	268	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2146	0	0
T12	27759	12	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	31	0	0
T130	0	31	0	0
T133	0	7	0	0
T144	0	82	0	0
T158	0	34	0	0
T170	0	33	0	0
T171	0	20	0	0
T172	0	242	0	0
T173	0	4	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2216	0	0
T12	27759	33	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	29	0	0
T130	0	7	0	0
T133	0	4	0	0
T144	0	79	0	0
T158	0	36	0	0
T170	0	13	0	0
T171	0	17	0	0
T172	0	256	0	0
T180	0	3	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2229	0	0
T12	27759	37	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T109	0	195	0	0
T116	0	31	0	0
T130	0	34	0	0
T144	0	69	0	0
T158	0	43	0	0
T170	0	33	0	0
T171	0	25	0	0
T172	0	222	0	0
T181	0	14	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2265	0	0
T12	27759	25	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	35	0	0
T130	0	77	0	0
T133	0	1	0	0
T144	0	87	0	0
T158	0	32	0	0
T170	0	59	0	0
T171	0	32	0	0
T172	0	222	0	0
T173	0	3	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2254	0	0
T12	27759	35	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	26	0	0
T130	0	59	0	0
T133	0	1	0	0
T144	0	94	0	0
T158	0	51	0	0
T170	0	17	0	0
T171	0	34	0	0
T172	0	228	0	0
T173	0	13	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2332	0	0
T12	27759	21	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T109	0	212	0	0
T116	0	36	0	0
T130	0	24	0	0
T144	0	67	0	0
T158	0	34	0	0
T170	0	31	0	0
T171	0	50	0	0
T172	0	244	0	0
T173	0	9	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2239	0	0
T12	27759	32	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	37	0	0
T130	0	17	0	0
T133	0	6	0	0
T144	0	77	0	0
T158	0	46	0	0
T170	0	30	0	0
T171	0	23	0	0
T172	0	276	0	0
T173	0	8	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2203	0	0
T12	27759	30	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T109	0	219	0	0
T116	0	23	0	0
T130	0	9	0	0
T144	0	79	0	0
T158	0	33	0	0
T170	0	24	0	0
T171	0	36	0	0
T172	0	219	0	0
T173	0	16	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24165812	2247	0	0
T12	27759	18	0	0
T13	32268	0	0	0
T14	2847	0	0	0
T15	85574	0	0	0
T16	7724	0	0	0
T33	8529	0	0	0
T34	11424	0	0	0
T45	77206	0	0	0
T79	4980	0	0	0
T80	5751	0	0	0
T116	0	18	0	0
T130	0	58	0	0
T133	0	3	0	0
T144	0	53	0	0
T158	0	30	0	0
T170	0	20	0	0
T171	0	41	0	0
T172	0	268	0	0
T173	0	2	0	0