Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2921555	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

595906

1

T1

129

T2

681

T3

1568

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3111471	1			T1	251		T2	782		T3	1562
values[0x0]	201649	1			T1	65		T2	268		T3	493
values[0x1]	204341	1			T1	65		T2	247		T3	545

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2004531	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1512930

1

T1

186

T2

821

T3

1834

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10815	1			T12	3		T13	2		T14	5
valid_sources[0x01]	11905	1			T2	6		T12	8		T13	1
valid_sources[0x02]	11159	1			T2	1		T3	16		T5	34
valid_sources[0x03]	11357	1			T2	8		T3	25		T13	3
valid_sources[0x04]	13605	1			T2	5		T13	5		T14	5
valid_sources[0x05]	12324	1			T2	17		T12	4		T13	6
valid_sources[0x06]	11937	1			T2	7		T4	32		T13	2
valid_sources[0x07]	12069	1			T1	6		T2	1		T12	1
valid_sources[0x08]	11540	1			T2	6		T5	29		T13	4
valid_sources[0x09]	10805	1			T1	6		T2	1		T13	2
valid_sources[0x0a]	11679	1			T5	50		T13	3		T14	10
valid_sources[0x0b]	11127	1			T1	6		T3	14		T13	2
valid_sources[0x0c]	11247	1			T1	3		T2	8		T4	122
valid_sources[0x0d]	12772	1			T2	7		T13	5		T14	13
valid_sources[0x0e]	11512	1			T2	7		T12	7		T13	3
valid_sources[0x0f]	12848	1			T2	6		T13	4		T14	12
valid_sources[0x10]	12405	1			T13	3		T14	11		T16	21
valid_sources[0x11]	13671	1			T2	5		T13	6		T14	11
valid_sources[0x12]	10782	1			T2	7		T5	8		T13	1
valid_sources[0x13]	11045	1			T2	1		T14	13		T16	1
valid_sources[0x14]	13649	1			T2	3		T12	10		T13	2
valid_sources[0x15]	10786	1			T1	9		T2	7		T13	2
valid_sources[0x16]	11244	1			T1	2		T3	27		T13	6
valid_sources[0x17]	12005	1			T2	1		T3	121		T5	3
valid_sources[0x18]	10939	1			T1	12		T2	5		T12	2
valid_sources[0x19]	11297	1			T2	10		T3	60		T12	2
valid_sources[0x1a]	12016	1			T1	1		T2	9		T13	3
valid_sources[0x1b]	10653	1			T2	3		T12	6		T13	5
valid_sources[0x1c]	12003	1			T2	1		T5	41		T12	2
valid_sources[0x1d]	14002	1			T2	19		T13	3		T14	16
valid_sources[0x1e]	11476	1			T2	9		T13	1		T14	11
valid_sources[0x1f]	15675	1			T1	7		T2	4		T12	11
valid_sources[0x20]	12480	1			T1	6		T2	7		T13	2
valid_sources[0x21]	11169	1			T2	2		T4	29		T13	1
valid_sources[0x22]	11837	1			T2	6		T3	68		T13	2
valid_sources[0x23]	11382	1			T2	10		T3	14		T13	3
valid_sources[0x24]	16508	1			T2	2		T4	2		T13	1
valid_sources[0x25]	17937	1			T1	2		T2	3		T12	22
valid_sources[0x26]	13453	1			T1	2		T2	5		T12	2
valid_sources[0x27]	11538	1			T2	7		T3	66		T12	5
valid_sources[0x28]	11647	1			T2	7		T13	3		T14	13
valid_sources[0x29]	13084	1			T12	3		T13	1		T14	8
valid_sources[0x2a]	15597	1			T1	5		T2	8		T3	87
valid_sources[0x2b]	11543	1			T3	8		T12	11		T13	3
valid_sources[0x2c]	11361	1			T12	1		T13	3		T14	8
valid_sources[0x2d]	12304	1			T1	1		T2	14		T5	7
valid_sources[0x2e]	13774	1			T2	2		T13	3		T14	10
valid_sources[0x2f]	13370	1			T2	14		T12	3		T13	4
valid_sources[0x30]	10698	1			T2	4		T3	20		T12	3
valid_sources[0x31]	12327	1			T1	2		T2	3		T12	3
valid_sources[0x32]	10654	1			T2	3		T12	2		T13	4
valid_sources[0x33]	11963	1			T2	14		T4	44		T12	3
valid_sources[0x34]	11294	1			T2	7		T13	2		T14	5
valid_sources[0x35]	11456	1			T2	5		T12	3		T13	2
valid_sources[0x36]	11151	1			T1	1		T2	2		T12	6
valid_sources[0x37]	11921	1			T2	4		T5	4		T14	6
valid_sources[0x38]	11625	1			T13	3		T14	8		T16	5
valid_sources[0x39]	14905	1			T2	11		T13	1		T14	9
valid_sources[0x3a]	18940	1			T2	1		T13	2		T14	12
valid_sources[0x3b]	12397	1			T1	3		T2	7		T3	155
valid_sources[0x3c]	11918	1			T2	2		T13	1		T14	7
valid_sources[0x3d]	11925	1			T2	4		T3	94		T13	3
valid_sources[0x3e]	12409	1			T1	2		T4	16		T13	2
valid_sources[0x3f]	12309	1			T13	5		T14	5		T16	4
valid_sources[0x40]	11098	1			T1	2		T2	6		T12	2
valid_sources[0x41]	11891	1			T13	5		T14	9		T15	502
valid_sources[0x42]	12531	1			T2	6		T3	47		T14	11
valid_sources[0x43]	11385	1			T2	14		T3	11		T13	2
valid_sources[0x44]	10725	1			T2	4		T3	56		T4	4
valid_sources[0x45]	12074	1			T1	11		T2	5		T4	29
valid_sources[0x46]	17912	1			T2	14		T3	38		T13	6
valid_sources[0x47]	11542	1			T2	9		T4	16		T12	3
valid_sources[0x48]	11373	1			T2	7		T3	13		T12	4
valid_sources[0x49]	11305	1			T2	4		T12	3		T13	2
valid_sources[0x4a]	10584	1			T2	13		T4	10		T13	4
valid_sources[0x4b]	11812	1			T2	7		T3	12		T13	2
valid_sources[0x4c]	15171	1			T2	4		T12	4		T13	1
valid_sources[0x4d]	15340	1			T2	2		T12	4		T14	14
valid_sources[0x4e]	11444	1			T2	2		T12	23		T13	3
valid_sources[0x4f]	11830	1			T2	7		T3	14		T12	2
valid_sources[0x50]	12443	1			T12	9		T13	7		T14	6
valid_sources[0x51]	11790	1			T1	2		T13	2		T14	9
valid_sources[0x52]	11562	1			T2	13		T13	1		T14	10
valid_sources[0x53]	11999	1			T2	19		T13	2		T14	12
valid_sources[0x54]	17996	1			T2	1		T12	3		T13	2
valid_sources[0x55]	11829	1			T1	1		T2	3		T12	6
valid_sources[0x56]	11041	1			T2	4		T13	4		T14	19
valid_sources[0x57]	23892	1			T2	4		T13	4		T14	8
valid_sources[0x58]	11259	1			T2	2		T3	8		T14	15
valid_sources[0x59]	17275	1			T2	1		T12	7		T13	2
valid_sources[0x5a]	11414	1			T2	8		T12	3		T14	12
valid_sources[0x5b]	11697	1			T1	12		T2	1		T13	2
valid_sources[0x5c]	11109	1			T1	2		T2	2		T3	41
valid_sources[0x5d]	17279	1			T2	5		T12	1		T13	2
valid_sources[0x5e]	10964	1			T2	2		T13	2		T14	6
valid_sources[0x5f]	25518	1			T1	1		T2	5		T12	2
valid_sources[0x60]	12956	1			T1	11		T2	4		T12	8
valid_sources[0x61]	13822	1			T2	4		T13	2		T14	14
valid_sources[0x62]	12078	1			T2	3		T12	3		T14	9
valid_sources[0x63]	11343	1			T2	3		T13	2		T14	14
valid_sources[0x64]	11164	1			T2	2		T4	95		T12	8
valid_sources[0x65]	19190	1			T2	14		T5	16		T12	3
valid_sources[0x66]	11700	1			T2	9		T13	1		T14	13
valid_sources[0x67]	11272	1			T2	3		T5	58		T13	2
valid_sources[0x68]	14103	1			T1	11		T2	6		T13	1
valid_sources[0x69]	28520	1			T2	7		T13	2		T14	11
valid_sources[0x6a]	12906	1			T2	4		T3	24		T12	3
valid_sources[0x6b]	11297	1			T2	6		T3	21		T12	2
valid_sources[0x6c]	12121	1			T2	5		T13	2		T14	15
valid_sources[0x6d]	11065	1			T1	7		T2	4		T3	4
valid_sources[0x6e]	11317	1			T1	6		T2	5		T12	6
valid_sources[0x6f]	11238	1			T1	13		T2	2		T3	13
valid_sources[0x70]	12578	1			T12	1		T13	2		T14	9
valid_sources[0x71]	11901	1			T2	6		T14	10		T32	1
valid_sources[0x72]	11326	1			T2	7		T13	1		T14	12
valid_sources[0x73]	12330	1			T2	3		T3	12		T12	1
valid_sources[0x74]	11494	1			T2	8		T12	5		T13	3
valid_sources[0x75]	11375	1			T2	6		T13	2		T14	10
valid_sources[0x76]	14125	1			T1	2		T2	2		T3	81
valid_sources[0x77]	13294	1			T12	8		T13	4		T14	10
valid_sources[0x78]	16426	1			T2	5		T12	4		T13	2
valid_sources[0x79]	10932	1			T1	2		T2	2		T4	8
valid_sources[0x7a]	20340	1			T1	2		T2	1		T13	3
valid_sources[0x7b]	18634	1			T2	3		T12	3		T13	3
valid_sources[0x7c]	11131	1			T2	26		T13	1		T14	12
valid_sources[0x7d]	10886	1			T2	1		T13	3		T14	8
valid_sources[0x7e]	12336	1			T1	1		T2	6		T12	2
valid_sources[0x7f]	14864	1			T3	21		T13	3		T14	7
valid_sources[0x80]	10900	1			T2	4		T13	2		T14	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

320686

1

T1

91

T2

294

T3

798

values[0x0]

all_enables

biggest_size

144846

1

T1

27

T2

203

T3

386

values[0x1]

all_enables

biggest_size

130374

1

T1

11

T2

184

T3

384