Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
22922428 |
22751236 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22922428 |
22751236 |
0 |
0 |
T1 |
5252 |
5098 |
0 |
0 |
T2 |
12394 |
12315 |
0 |
0 |
T3 |
22505 |
22386 |
0 |
0 |
T4 |
3454 |
3396 |
0 |
0 |
T5 |
3920 |
3749 |
0 |
0 |
T12 |
6348 |
6260 |
0 |
0 |
T13 |
8263 |
8122 |
0 |
0 |
T14 |
7603 |
7476 |
0 |
0 |
T15 |
6174 |
6102 |
0 |
0 |
T16 |
15304 |
15248 |
0 |
0 |