Module Definition
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Module : keymgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.keymgr_csr_assert 100.00 100.00


Module Instance : tb.dut.keymgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : keymgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 24660029 15707 0 0
attest_sw_binding_0_rd_A 24660029 2229 0 0
attest_sw_binding_1_rd_A 24660029 2228 0 0
attest_sw_binding_2_rd_A 24660029 2254 0 0
attest_sw_binding_3_rd_A 24660029 2228 0 0
attest_sw_binding_4_rd_A 24660029 2397 0 0
attest_sw_binding_5_rd_A 24660029 2357 0 0
attest_sw_binding_6_rd_A 24660029 2136 0 0
attest_sw_binding_7_rd_A 24660029 2133 0 0
intr_enable_rd_A 24660029 2886 0 0
key_version_rd_A 24660029 2216 0 0
max_creator_key_ver_regwen_rd_A 24660029 2101 0 0
max_owner_int_key_ver_regwen_rd_A 24660029 2288 0 0
max_owner_key_ver_regwen_rd_A 24660029 2077 0 0
reseed_interval_regwen_rd_A 24660029 2159 0 0
salt_0_rd_A 24660029 2325 0 0
salt_1_rd_A 24660029 2181 0 0
salt_2_rd_A 24660029 2253 0 0
salt_3_rd_A 24660029 2294 0 0
salt_4_rd_A 24660029 2215 0 0
salt_5_rd_A 24660029 2187 0 0
salt_6_rd_A 24660029 2172 0 0
salt_7_rd_A 24660029 2170 0 0
sealing_sw_binding_0_rd_A 24660029 2120 0 0
sealing_sw_binding_1_rd_A 24660029 2222 0 0
sealing_sw_binding_2_rd_A 24660029 2250 0 0
sealing_sw_binding_3_rd_A 24660029 2294 0 0
sealing_sw_binding_4_rd_A 24660029 2167 0 0
sealing_sw_binding_5_rd_A 24660029 2119 0 0
sealing_sw_binding_6_rd_A 24660029 2081 0 0
sealing_sw_binding_7_rd_A 24660029 2209 0 0
sideload_clear_rd_A 24660029 2162 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 15707 0 0
T3 22505 127 0 0
T4 3454 0 0 0
T5 3920 0 0 0
T12 6348 0 0 0
T13 8263 0 0 0
T14 7603 0 0 0
T15 6174 0 0 0
T16 15304 0 0 0
T32 7366 0 0 0
T41 0 162 0 0
T52 0 541 0 0
T57 0 170 0 0
T61 0 35 0 0
T71 0 720 0 0
T72 0 100 0 0
T74 0 292 0 0
T94 1100 0 0 0
T112 0 125 0 0
T130 0 319 0 0

attest_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2229 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 26 0 0
T72 0 35 0 0
T127 0 20 0 0
T137 0 5 0 0
T152 0 37 0 0
T153 0 60 0 0
T154 0 64 0 0
T155 0 17 0 0
T156 0 4 0 0
T157 0 16 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0

attest_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2228 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 22 0 0
T72 0 50 0 0
T127 0 15 0 0
T152 0 61 0 0
T153 0 56 0 0
T154 0 53 0 0
T155 0 16 0 0
T156 0 9 0 0
T157 0 9 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 4 0 0

attest_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2254 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 25 0 0
T72 0 58 0 0
T127 0 25 0 0
T152 0 51 0 0
T153 0 56 0 0
T154 0 42 0 0
T155 0 26 0 0
T156 0 38 0 0
T157 0 4 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 7 0 0

attest_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2228 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 27 0 0
T72 0 53 0 0
T127 0 23 0 0
T152 0 56 0 0
T153 0 89 0 0
T154 0 69 0 0
T155 0 40 0 0
T156 0 8 0 0
T157 0 13 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 16 0 0

attest_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2397 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 25 0 0
T72 0 45 0 0
T127 0 31 0 0
T137 0 17 0 0
T152 0 37 0 0
T153 0 63 0 0
T154 0 32 0 0
T155 0 50 0 0
T156 0 24 0 0
T157 0 8 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0

attest_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2357 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 34 0 0
T72 0 41 0 0
T127 0 12 0 0
T152 0 51 0 0
T153 0 84 0 0
T154 0 40 0 0
T155 0 47 0 0
T156 0 25 0 0
T157 0 14 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 18 0 0

attest_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2136 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 11 0 0
T72 0 69 0 0
T127 0 13 0 0
T137 0 9 0 0
T152 0 50 0 0
T153 0 44 0 0
T154 0 68 0 0
T155 0 34 0 0
T156 0 18 0 0
T157 0 8 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0

attest_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2133 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 20 0 0
T72 0 74 0 0
T127 0 17 0 0
T152 0 26 0 0
T153 0 60 0 0
T154 0 55 0 0
T155 0 17 0 0
T156 0 16 0 0
T157 0 10 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 9 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2886 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T48 0 7 0 0
T51 0 25 0 0
T61 22693 36 0 0
T72 0 58 0 0
T77 0 17 0 0
T152 0 87 0 0
T153 0 80 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T166 0 16 0 0
T167 0 11 0 0
T168 0 24 0 0

key_version_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2216 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 7 0 0
T72 0 39 0 0
T127 0 22 0 0
T152 0 60 0 0
T153 0 76 0 0
T154 0 70 0 0
T155 0 47 0 0
T156 0 5 0 0
T157 0 10 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 3 0 0

max_creator_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2101 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 17 0 0
T72 0 63 0 0
T127 0 17 0 0
T152 0 21 0 0
T153 0 87 0 0
T154 0 54 0 0
T155 0 23 0 0
T156 0 9 0 0
T157 0 2 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 16 0 0

max_owner_int_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2288 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 40 0 0
T72 0 71 0 0
T152 0 28 0 0
T153 0 55 0 0
T154 0 46 0 0
T155 0 36 0 0
T156 0 15 0 0
T157 0 15 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 6 0 0
T169 0 1 0 0

max_owner_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2077 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 19 0 0
T72 0 43 0 0
T127 0 15 0 0
T152 0 30 0 0
T153 0 71 0 0
T154 0 51 0 0
T155 0 29 0 0
T156 0 9 0 0
T157 0 10 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 1 0 0

reseed_interval_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2159 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 29 0 0
T72 0 68 0 0
T127 0 18 0 0
T137 0 11 0 0
T152 0 37 0 0
T153 0 70 0 0
T154 0 63 0 0
T155 0 17 0 0
T156 0 5 0 0
T157 0 6 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0

salt_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2325 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 15 0 0
T72 0 54 0 0
T127 0 20 0 0
T152 0 48 0 0
T153 0 75 0 0
T154 0 72 0 0
T155 0 32 0 0
T156 0 24 0 0
T157 0 10 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T170 0 5 0 0

salt_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2181 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 11 0 0
T72 0 78 0 0
T127 0 21 0 0
T152 0 36 0 0
T153 0 72 0 0
T154 0 36 0 0
T155 0 27 0 0
T156 0 23 0 0
T157 0 12 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 13 0 0

salt_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2253 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 16 0 0
T72 0 77 0 0
T127 0 15 0 0
T137 0 8 0 0
T152 0 45 0 0
T153 0 88 0 0
T154 0 66 0 0
T155 0 44 0 0
T156 0 17 0 0
T157 0 6 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0

salt_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2294 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 35 0 0
T72 0 53 0 0
T127 0 20 0 0
T137 0 13 0 0
T152 0 34 0 0
T153 0 61 0 0
T154 0 61 0 0
T155 0 21 0 0
T157 0 6 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 8 0 0

salt_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2215 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 33 0 0
T72 0 47 0 0
T127 0 20 0 0
T152 0 28 0 0
T153 0 79 0 0
T154 0 47 0 0
T155 0 28 0 0
T156 0 21 0 0
T157 0 7 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 9 0 0

salt_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2187 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 39 0 0
T72 0 52 0 0
T127 0 15 0 0
T152 0 34 0 0
T153 0 66 0 0
T154 0 70 0 0
T155 0 33 0 0
T156 0 8 0 0
T157 0 5 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 9 0 0

salt_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2172 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 26 0 0
T72 0 60 0 0
T127 0 16 0 0
T152 0 27 0 0
T153 0 63 0 0
T154 0 53 0 0
T155 0 34 0 0
T156 0 5 0 0
T157 0 6 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 7 0 0

salt_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2170 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 23 0 0
T72 0 58 0 0
T127 0 19 0 0
T152 0 37 0 0
T153 0 76 0 0
T154 0 43 0 0
T155 0 44 0 0
T156 0 6 0 0
T157 0 14 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 8 0 0

sealing_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2120 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 29 0 0
T72 0 58 0 0
T127 0 12 0 0
T152 0 38 0 0
T153 0 46 0 0
T154 0 52 0 0
T155 0 23 0 0
T156 0 2 0 0
T157 0 10 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T171 0 3 0 0

sealing_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2222 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 18 0 0
T72 0 53 0 0
T127 0 20 0 0
T137 0 8 0 0
T152 0 29 0 0
T153 0 72 0 0
T154 0 50 0 0
T155 0 30 0 0
T156 0 13 0 0
T157 0 6 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0

sealing_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2250 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 27 0 0
T72 0 46 0 0
T127 0 20 0 0
T137 0 12 0 0
T152 0 21 0 0
T153 0 72 0 0
T154 0 52 0 0
T155 0 41 0 0
T156 0 16 0 0
T157 0 5 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0

sealing_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2294 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 25 0 0
T72 0 46 0 0
T127 0 21 0 0
T152 0 43 0 0
T153 0 67 0 0
T154 0 70 0 0
T155 0 6 0 0
T156 0 21 0 0
T157 0 2 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 9 0 0

sealing_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2167 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 11 0 0
T72 0 60 0 0
T127 0 28 0 0
T152 0 26 0 0
T153 0 71 0 0
T154 0 83 0 0
T155 0 12 0 0
T156 0 30 0 0
T157 0 10 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 9 0 0

sealing_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2119 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 9 0 0
T72 0 49 0 0
T152 0 36 0 0
T153 0 55 0 0
T154 0 43 0 0
T155 0 37 0 0
T156 0 3 0 0
T157 0 4 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 7 0 0
T172 0 1 0 0

sealing_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2081 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 16 0 0
T72 0 34 0 0
T127 0 20 0 0
T152 0 43 0 0
T153 0 55 0 0
T154 0 63 0 0
T155 0 9 0 0
T156 0 15 0 0
T157 0 6 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 12 0 0

sealing_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2209 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 25 0 0
T72 0 59 0 0
T127 0 11 0 0
T152 0 54 0 0
T153 0 62 0 0
T154 0 63 0 0
T155 0 19 0 0
T156 0 12 0 0
T157 0 1 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 1 0 0

sideload_clear_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24660029 2162 0 0
T18 8408 0 0 0
T24 22421 0 0 0
T61 22693 20 0 0
T72 0 40 0 0
T127 0 15 0 0
T152 0 43 0 0
T153 0 72 0 0
T154 0 30 0 0
T155 0 35 0 0
T156 0 14 0 0
T157 0 11 0 0
T158 219641 0 0 0
T159 8420 0 0 0
T160 3059 0 0 0
T161 58541 0 0 0
T162 9648 0 0 0
T163 964 0 0 0
T164 6755 0 0 0
T165 0 5 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%