Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3251355	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

644286

1

T1

6

T2

156

T3

282

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3485493	1			T1	1		T2	775		T3	2041
values[0x0]	203747	1			T1	10		T2	39		T3	119
values[0x1]	206401	1			T1	10		T2	48		T3	89

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2229967	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1665674

1

T1

6

T2

358

T3

870

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13730	1			T5	1		T14	11		T15	2
valid_sources[0x01]	11423	1			T2	2		T5	2		T15	2
valid_sources[0x02]	12919	1			T5	4		T6	2		T16	2
valid_sources[0x03]	12360	1			T2	8		T5	2		T14	21
valid_sources[0x04]	11521	1			T5	4		T14	1		T15	3
valid_sources[0x05]	11766	1			T2	2		T15	2		T6	4
valid_sources[0x06]	13535	1			T5	1		T14	9		T15	2
valid_sources[0x07]	11530	1			T5	3		T14	1		T15	1
valid_sources[0x08]	13908	1			T5	2		T14	5		T6	7
valid_sources[0x09]	14000	1			T1	1		T5	2		T15	2
valid_sources[0x0a]	10975	1			T2	17		T14	8		T15	4
valid_sources[0x0b]	23981	1			T1	3		T2	4		T5	2
valid_sources[0x0c]	12028	1			T14	3		T15	1		T6	5
valid_sources[0x0d]	11252	1			T5	1		T14	5		T15	3
valid_sources[0x0e]	12934	1			T2	5		T5	1		T6	6
valid_sources[0x0f]	11424	1			T2	3		T5	3		T14	22
valid_sources[0x10]	15739	1			T2	1		T5	4		T6	3
valid_sources[0x11]	17093	1			T2	20		T5	2		T15	1
valid_sources[0x12]	11150	1			T5	3		T14	3		T15	6
valid_sources[0x13]	22264	1			T2	1		T5	1		T14	17
valid_sources[0x14]	12396	1			T5	3		T14	4		T15	2
valid_sources[0x15]	12808	1			T5	4		T15	1		T6	3
valid_sources[0x16]	11876	1			T2	20		T5	1		T14	3
valid_sources[0x17]	13318	1			T2	18		T5	5		T14	15
valid_sources[0x18]	12053	1			T5	2		T14	3		T15	2
valid_sources[0x19]	14642	1			T5	1		T14	11		T15	1
valid_sources[0x1a]	19816	1			T14	6		T6	7		T16	1
valid_sources[0x1b]	48409	1			T2	1		T5	3		T15	3
valid_sources[0x1c]	44473	1			T5	4		T15	3		T6	5
valid_sources[0x1d]	12287	1			T5	3		T15	1		T6	3
valid_sources[0x1e]	14738	1			T2	13		T5	3		T14	16
valid_sources[0x1f]	11603	1			T14	8		T6	4		T16	4
valid_sources[0x20]	11130	1			T2	16		T14	6		T6	4
valid_sources[0x21]	13876	1			T5	2		T14	1		T15	1
valid_sources[0x22]	12546	1			T2	23		T5	4		T15	4
valid_sources[0x23]	11608	1			T5	6		T15	1		T6	3
valid_sources[0x24]	14460	1			T14	9		T15	5		T6	2
valid_sources[0x25]	12743	1			T5	4		T14	2		T15	1
valid_sources[0x26]	15951	1			T5	2		T15	5		T6	2
valid_sources[0x27]	13553	1			T5	3		T14	1		T6	3
valid_sources[0x28]	11731	1			T2	27		T5	4		T14	31
valid_sources[0x29]	11696	1			T5	2		T14	1		T15	2
valid_sources[0x2a]	10348	1			T5	3		T14	5		T15	1
valid_sources[0x2b]	12170	1			T5	2		T14	7		T15	2
valid_sources[0x2c]	11804	1			T14	23		T6	9		T16	2
valid_sources[0x2d]	10827	1			T2	1		T5	2		T15	4
valid_sources[0x2e]	11443	1			T5	6		T14	11		T15	1
valid_sources[0x2f]	11252	1			T1	1		T2	18		T5	2
valid_sources[0x30]	11147	1			T5	5		T14	15		T15	2
valid_sources[0x31]	27472	1			T5	2		T15	2		T6	5
valid_sources[0x32]	23786	1			T2	4		T5	2		T14	5
valid_sources[0x33]	12701	1			T5	1		T14	4		T15	1
valid_sources[0x34]	14847	1			T2	1		T5	6		T6	3
valid_sources[0x35]	14225	1			T5	3		T14	4		T15	1
valid_sources[0x36]	14391	1			T2	3		T5	3		T14	1
valid_sources[0x37]	14204	1			T5	3		T14	9		T15	2
valid_sources[0x38]	11729	1			T5	3		T14	13		T6	5
valid_sources[0x39]	12821	1			T1	1		T5	1		T14	13
valid_sources[0x3a]	12704	1			T2	2		T14	3		T15	1
valid_sources[0x3b]	16249	1			T2	9		T5	5		T14	7
valid_sources[0x3c]	28352	1			T2	7		T5	2		T14	6
valid_sources[0x3d]	13659	1			T2	5		T5	3		T14	5
valid_sources[0x3e]	15998	1			T2	2		T5	2		T14	4
valid_sources[0x3f]	12825	1			T2	17		T14	23		T6	4
valid_sources[0x40]	13259	1			T2	2		T5	2		T14	9
valid_sources[0x41]	16039	1			T5	1		T14	8		T6	5
valid_sources[0x42]	11862	1			T14	12		T6	4		T16	1
valid_sources[0x43]	14223	1			T5	2		T14	7		T15	3
valid_sources[0x44]	11783	1			T2	2		T5	4		T14	2
valid_sources[0x45]	13050	1			T2	6		T5	2		T14	2
valid_sources[0x46]	15235	1			T5	2		T14	7		T6	5
valid_sources[0x47]	17520	1			T4	1449		T5	2		T14	1
valid_sources[0x48]	12019	1			T2	20		T5	3		T14	19
valid_sources[0x49]	26084	1			T1	1		T2	2		T5	1
valid_sources[0x4a]	12580	1			T5	5		T6	3		T17	8
valid_sources[0x4b]	13620	1			T5	3		T14	1		T15	1
valid_sources[0x4c]	12322	1			T2	10		T5	3		T14	10
valid_sources[0x4d]	15653	1			T5	1		T14	8		T6	4
valid_sources[0x4e]	11546	1			T2	11		T5	1		T14	6
valid_sources[0x4f]	11835	1			T14	5		T15	1		T6	5
valid_sources[0x50]	12983	1			T2	11		T5	2		T14	11
valid_sources[0x51]	16391	1			T1	1		T2	17		T5	2
valid_sources[0x52]	11431	1			T5	1		T14	7		T15	5
valid_sources[0x53]	12567	1			T2	2		T5	2		T14	10
valid_sources[0x54]	26330	1			T3	2249		T5	1		T14	1
valid_sources[0x55]	41168	1			T2	2		T5	6		T14	7
valid_sources[0x56]	11136	1			T2	3		T5	3		T14	3
valid_sources[0x57]	10931	1			T5	1		T15	2		T6	4
valid_sources[0x58]	13130	1			T2	9		T5	7		T14	9
valid_sources[0x59]	11661	1			T5	1		T14	1		T15	1
valid_sources[0x5a]	13771	1			T2	4		T5	3		T14	2
valid_sources[0x5b]	11612	1			T2	8		T5	4		T14	1
valid_sources[0x5c]	11397	1			T2	4		T5	1		T14	2
valid_sources[0x5d]	11164	1			T5	3		T14	11		T15	1
valid_sources[0x5e]	12841	1			T5	2		T14	8		T15	2
valid_sources[0x5f]	16022	1			T2	1		T5	3		T14	14
valid_sources[0x60]	13215	1			T5	3		T14	3		T6	3
valid_sources[0x61]	16138	1			T5	2		T14	7		T15	1
valid_sources[0x62]	16269	1			T5	7		T15	6		T16	3
valid_sources[0x63]	12063	1			T5	1		T14	10		T15	3
valid_sources[0x64]	17967	1			T15	4		T6	2		T16	1
valid_sources[0x65]	11449	1			T5	3		T14	9		T15	3
valid_sources[0x66]	13571	1			T2	1		T5	3		T14	1
valid_sources[0x67]	13384	1			T2	1		T14	1		T15	1
valid_sources[0x68]	11443	1			T14	24		T15	2		T6	7
valid_sources[0x69]	11270	1			T2	13		T5	5		T14	7
valid_sources[0x6a]	12226	1			T2	6		T5	1		T14	1
valid_sources[0x6b]	13641	1			T6	3		T17	10		T32	2
valid_sources[0x6c]	17527	1			T2	3		T5	1		T6	5
valid_sources[0x6d]	17083	1			T2	18		T5	3		T14	11
valid_sources[0x6e]	11432	1			T5	5		T14	10		T15	2
valid_sources[0x6f]	10905	1			T5	4		T14	6		T15	4
valid_sources[0x70]	11117	1			T14	10		T6	8		T16	7
valid_sources[0x71]	13491	1			T5	5		T15	3		T6	7
valid_sources[0x72]	12087	1			T1	2		T14	19		T15	1
valid_sources[0x73]	39540	1			T2	20		T5	1		T15	1
valid_sources[0x74]	11730	1			T5	3		T14	13		T6	3
valid_sources[0x75]	11168	1			T5	1		T15	3		T6	6
valid_sources[0x76]	21723	1			T14	6		T6	6		T16	8
valid_sources[0x77]	11310	1			T1	2		T2	1		T5	1
valid_sources[0x78]	15430	1			T5	1		T14	2		T15	2
valid_sources[0x79]	15933	1			T2	4		T5	1		T15	2
valid_sources[0x7a]	11570	1			T5	2		T14	3		T15	2
valid_sources[0x7b]	12310	1			T2	6		T5	1		T15	1
valid_sources[0x7c]	14462	1			T2	2		T14	4		T15	1
valid_sources[0x7d]	10781	1			T14	6		T6	7		T16	3
valid_sources[0x7e]	18544	1			T5	1		T14	3		T15	4
valid_sources[0x7f]	12834	1			T14	19		T6	9		T16	2
valid_sources[0x80]	13016	1			T2	8		T5	4		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

363728

1

T1

1

T2

127

T3

160

values[0x0]

all_enables

biggest_size

147469

1

T1

3

T2

21

T3

79

values[0x1]

all_enables

biggest_size

133089

1

T1

2

T2

8

T3

43