Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2986293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

621840

1

T1

7

T2

553

T3

156

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3188004	1			T1	1		T2	1028		T3	107
values[0x0]	208869	1			T1	15		T2	250		T3	60
values[0x1]	211260	1			T1	13		T2	242		T3	75

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2051403	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1556730

1

T1

8

T2

799

T3

182

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10492	1			T2	5		T4	2		T5	5
valid_sources[0x01]	12557	1			T2	11		T4	8		T5	1
valid_sources[0x02]	11266	1			T2	14		T5	8		T15	1
valid_sources[0x03]	12163	1			T2	8		T5	4		T15	1
valid_sources[0x04]	10513	1			T2	3		T5	3		T15	1
valid_sources[0x05]	11024	1			T2	11		T5	1		T15	1
valid_sources[0x06]	10055	1			T2	4		T5	3		T15	1
valid_sources[0x07]	14297	1			T2	5		T4	3		T5	3
valid_sources[0x08]	11297	1			T2	7		T5	3		T15	2
valid_sources[0x09]	11774	1			T2	10		T5	2		T18	5
valid_sources[0x0a]	10336	1			T2	3		T5	3		T15	3
valid_sources[0x0b]	11993	1			T2	5		T5	7		T15	2
valid_sources[0x0c]	12143	1			T4	10		T5	2		T15	2
valid_sources[0x0d]	10259	1			T2	6		T5	6		T18	6
valid_sources[0x0e]	12593	1			T2	5		T5	1		T15	2
valid_sources[0x0f]	10763	1			T2	2		T5	1		T17	3
valid_sources[0x10]	10565	1			T2	7		T5	1		T15	2
valid_sources[0x11]	15897	1			T2	6		T17	1		T6	2
valid_sources[0x12]	10406	1			T2	4		T4	12		T5	3
valid_sources[0x13]	16247	1			T2	8		T4	1		T5	7
valid_sources[0x14]	10770	1			T2	9		T4	1		T5	2
valid_sources[0x15]	11188	1			T2	7		T5	9		T15	4
valid_sources[0x16]	10981	1			T2	3		T5	1		T15	2
valid_sources[0x17]	23685	1			T2	4		T15	5		T17	2
valid_sources[0x18]	34763	1			T2	3		T5	7		T18	1
valid_sources[0x19]	10277	1			T2	2		T5	5		T17	2
valid_sources[0x1a]	11520	1			T2	3		T15	2		T17	2
valid_sources[0x1b]	10266	1			T2	4		T5	2		T15	2
valid_sources[0x1c]	19074	1			T2	8		T4	1		T5	3
valid_sources[0x1d]	17673	1			T2	2		T5	3		T15	3
valid_sources[0x1e]	9913	1			T2	5		T5	2		T15	3
valid_sources[0x1f]	28548	1			T2	1		T4	9		T5	3
valid_sources[0x20]	10259	1			T2	3		T5	2		T15	1
valid_sources[0x21]	11539	1			T2	8		T5	3		T15	3
valid_sources[0x22]	10302	1			T2	8		T5	6		T18	4
valid_sources[0x23]	14983	1			T2	5		T4	3		T5	4
valid_sources[0x24]	10464	1			T1	29		T2	4		T4	2
valid_sources[0x25]	9878	1			T2	5		T5	2		T15	2
valid_sources[0x26]	10455	1			T2	9		T4	2		T5	4
valid_sources[0x27]	14226	1			T2	1		T5	1		T15	2
valid_sources[0x28]	11490	1			T2	5		T15	2		T17	2
valid_sources[0x29]	10615	1			T2	3		T4	1		T15	1
valid_sources[0x2a]	14540	1			T2	7		T5	2		T15	2
valid_sources[0x2b]	11734	1			T2	4		T5	5		T15	2
valid_sources[0x2c]	11046	1			T2	6		T17	4		T18	2
valid_sources[0x2d]	10480	1			T2	3		T5	3		T15	3
valid_sources[0x2e]	20477	1			T2	3		T4	1		T5	5
valid_sources[0x2f]	12338	1			T2	6		T4	1		T5	2
valid_sources[0x30]	12727	1			T2	8		T4	2		T5	15
valid_sources[0x31]	11007	1			T2	8		T4	6		T5	10
valid_sources[0x32]	10720	1			T2	13		T4	1		T15	3
valid_sources[0x33]	10432	1			T2	3		T5	3		T15	1
valid_sources[0x34]	10010	1			T5	5		T15	2		T17	2
valid_sources[0x35]	15798	1			T2	4		T4	11		T5	2
valid_sources[0x36]	12697	1			T2	9		T4	5		T5	5
valid_sources[0x37]	10933	1			T2	9		T4	5		T5	4
valid_sources[0x38]	28443	1			T2	3		T15	3		T18	7
valid_sources[0x39]	13653	1			T2	9		T5	4		T15	3
valid_sources[0x3a]	11239	1			T2	2		T15	1		T17	2
valid_sources[0x3b]	15671	1			T2	4		T15	2		T17	3
valid_sources[0x3c]	10667	1			T2	5		T15	1		T18	7
valid_sources[0x3d]	28858	1			T2	6		T5	1		T15	3
valid_sources[0x3e]	9951	1			T2	3		T5	12		T15	3
valid_sources[0x3f]	32943	1			T2	6		T5	6		T15	1
valid_sources[0x40]	14731	1			T2	15		T5	3		T15	5
valid_sources[0x41]	10202	1			T2	4		T4	3		T15	1
valid_sources[0x42]	11332	1			T2	4		T5	3		T15	1
valid_sources[0x43]	25869	1			T2	5		T5	3		T17	1
valid_sources[0x44]	36132	1			T2	6		T4	4		T5	8
valid_sources[0x45]	10604	1			T2	3		T4	5		T15	1
valid_sources[0x46]	10209	1			T2	5		T5	3		T15	3
valid_sources[0x47]	10301	1			T2	9		T5	2		T15	1
valid_sources[0x48]	15750	1			T2	3		T15	2		T18	2
valid_sources[0x49]	13655	1			T2	1		T5	1		T15	5
valid_sources[0x4a]	10289	1			T2	3		T5	4		T15	4
valid_sources[0x4b]	16245	1			T2	15		T4	3		T5	4
valid_sources[0x4c]	10760	1			T2	2		T4	9		T5	2
valid_sources[0x4d]	11344	1			T2	4		T4	22		T5	5
valid_sources[0x4e]	30974	1			T2	7		T15	1		T18	2
valid_sources[0x4f]	11442	1			T2	5		T5	4		T15	1
valid_sources[0x50]	10279	1			T2	3		T5	4		T15	2
valid_sources[0x51]	10656	1			T2	8		T4	2		T5	9
valid_sources[0x52]	24350	1			T2	3		T5	3		T15	1
valid_sources[0x53]	13350	1			T2	4		T5	2		T15	6
valid_sources[0x54]	10637	1			T2	7		T17	6		T6	6
valid_sources[0x55]	10492	1			T2	4		T15	3		T18	4
valid_sources[0x56]	17102	1			T2	7		T5	1		T15	3
valid_sources[0x57]	11779	1			T2	8		T4	9		T5	6
valid_sources[0x58]	11423	1			T2	8		T5	4		T17	2
valid_sources[0x59]	21576	1			T2	3		T5	2		T15	1
valid_sources[0x5a]	14729	1			T2	8		T4	4		T5	15
valid_sources[0x5b]	11299	1			T2	6		T5	2		T15	2
valid_sources[0x5c]	11270	1			T2	4		T15	1		T17	2
valid_sources[0x5d]	9861	1			T2	6		T4	2		T5	4
valid_sources[0x5e]	11152	1			T2	4		T15	4		T17	1
valid_sources[0x5f]	12120	1			T2	7		T5	9		T17	4
valid_sources[0x60]	10456	1			T2	7		T5	11		T15	1
valid_sources[0x61]	10236	1			T2	14		T4	3		T5	1
valid_sources[0x62]	11558	1			T2	3		T5	5		T15	1
valid_sources[0x63]	11086	1			T2	10		T4	7		T5	1
valid_sources[0x64]	11884	1			T2	7		T4	4		T5	7
valid_sources[0x65]	10738	1			T2	2		T4	6		T5	1
valid_sources[0x66]	10197	1			T2	2		T4	1		T15	2
valid_sources[0x67]	11510	1			T2	6		T4	14		T5	2
valid_sources[0x68]	11852	1			T2	4		T5	2		T15	3
valid_sources[0x69]	13266	1			T4	5		T5	3		T15	1
valid_sources[0x6a]	10780	1			T2	8		T4	2		T5	7
valid_sources[0x6b]	10412	1			T2	4		T4	8		T5	1
valid_sources[0x6c]	12453	1			T2	8		T4	1		T5	3
valid_sources[0x6d]	11673	1			T2	2		T5	4		T15	4
valid_sources[0x6e]	11441	1			T2	7		T5	3		T15	3
valid_sources[0x6f]	14818	1			T2	6		T4	1		T5	9
valid_sources[0x70]	10534	1			T2	9		T15	1		T17	2
valid_sources[0x71]	9840	1			T2	10		T4	4		T15	1
valid_sources[0x72]	12327	1			T2	7		T5	8		T17	1
valid_sources[0x73]	14539	1			T2	3		T4	3		T15	1
valid_sources[0x74]	11187	1			T2	3		T5	3		T15	2
valid_sources[0x75]	11068	1			T2	1		T5	3		T15	1
valid_sources[0x76]	12992	1			T2	8		T4	1		T5	4
valid_sources[0x77]	10982	1			T2	4		T5	1		T15	1
valid_sources[0x78]	11313	1			T2	6		T4	7		T5	7
valid_sources[0x79]	10762	1			T2	2		T15	1		T17	4
valid_sources[0x7a]	11598	1			T2	13		T15	3		T6	3
valid_sources[0x7b]	10915	1			T2	6		T5	1		T15	1
valid_sources[0x7c]	10562	1			T2	7		T4	1		T5	1
valid_sources[0x7d]	10399	1			T2	5		T5	6		T15	1
valid_sources[0x7e]	10428	1			T2	8		T5	7		T18	4
valid_sources[0x7f]	17352	1			T2	5		T5	1		T15	1
valid_sources[0x80]	11123	1			T2	3		T5	7		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

335241

1

T2

245

T3

43

T4

117

values[0x0]

all_enables

biggest_size

151196

1

T1

4

T2

173

T3

48

values[0x1]

all_enables

biggest_size

135403

1

T1

3

T2

135

T3

65