Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
22989009 |
22830770 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22989009 |
22830770 |
0 |
0 |
T1 |
1214 |
1129 |
0 |
0 |
T2 |
12281 |
12108 |
0 |
0 |
T3 |
3119 |
2970 |
0 |
0 |
T4 |
4830 |
4744 |
0 |
0 |
T5 |
7474 |
7408 |
0 |
0 |
T15 |
5797 |
5731 |
0 |
0 |
T16 |
3634 |
3552 |
0 |
0 |
T17 |
4870 |
4775 |
0 |
0 |
T18 |
7984 |
7885 |
0 |
0 |
T19 |
9375 |
9304 |
0 |
0 |