Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.94	96.00	97.81	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24738643	15381	0	0
attest_sw_binding_0_rd_A	24738643	2898	0	0
attest_sw_binding_1_rd_A	24738643	3061	0	0
attest_sw_binding_2_rd_A	24738643	3007	0	0
attest_sw_binding_3_rd_A	24738643	2762	0	0
attest_sw_binding_4_rd_A	24738643	2844	0	0
attest_sw_binding_5_rd_A	24738643	2909	0	0
attest_sw_binding_6_rd_A	24738643	2738	0	0
attest_sw_binding_7_rd_A	24738643	2963	0	0
intr_enable_rd_A	24738643	3662	0	0
key_version_rd_A	24738643	3047	0	0
max_creator_key_ver_regwen_rd_A	24738643	2895	0	0
max_owner_int_key_ver_regwen_rd_A	24738643	2690	0	0
max_owner_key_ver_regwen_rd_A	24738643	2905	0	0
reseed_interval_regwen_rd_A	24738643	2862	0	0
salt_0_rd_A	24738643	2859	0	0
salt_1_rd_A	24738643	3045	0	0
salt_2_rd_A	24738643	2807	0	0
salt_3_rd_A	24738643	2942	0	0
salt_4_rd_A	24738643	2819	0	0
salt_5_rd_A	24738643	2887	0	0
salt_6_rd_A	24738643	2930	0	0
salt_7_rd_A	24738643	3032	0	0
sealing_sw_binding_0_rd_A	24738643	2868	0	0
sealing_sw_binding_1_rd_A	24738643	2798	0	0
sealing_sw_binding_2_rd_A	24738643	2762	0	0
sealing_sw_binding_3_rd_A	24738643	2728	0	0
sealing_sw_binding_4_rd_A	24738643	2768	0	0
sealing_sw_binding_5_rd_A	24738643	2879	0	0
sealing_sw_binding_6_rd_A	24738643	2793	0	0
sealing_sw_binding_7_rd_A	24738643	3055	0	0
sideload_clear_rd_A	24738643	2882	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	15381	0	0
T9	0	752	0	0
T47	24302	0	0	0
T52	0	151	0	0
T55	9639	0	0	0
T59	16150	690	0	0
T70	0	241	0	0
T127	0	90	0	0
T128	0	212	0	0
T129	0	67	0	0
T130	0	225	0	0
T131	0	943	0	0
T132	0	507	0	0
T133	3525	0	0	0
T134	12186	0	0	0
T135	5199	0	0	0
T136	4932	0	0	0
T137	5594	0	0	0
T138	6191	0	0	0
T139	14770	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2898	0	0
T52	45964	80	0	0
T120	0	10	0	0
T127	36792	0	0	0
T128	0	72	0	0
T144	5262	0	0	0
T148	0	45	0	0
T186	0	35	0	0
T187	0	13	0	0
T188	0	15	0	0
T189	0	27	0	0
T190	0	29	0	0
T191	0	38	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	3061	0	0
T52	45964	70	0	0
T120	0	20	0	0
T127	36792	0	0	0
T128	0	71	0	0
T144	5262	0	0	0
T148	0	56	0	0
T186	0	46	0	0
T187	0	24	0	0
T188	0	17	0	0
T189	0	19	0	0
T190	0	32	0	0
T191	0	36	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	3007	0	0
T52	45964	62	0	0
T120	0	16	0	0
T127	36792	0	0	0
T128	0	40	0	0
T144	5262	0	0	0
T148	0	65	0	0
T186	0	38	0	0
T187	0	36	0	0
T188	0	17	0	0
T189	0	28	0	0
T190	0	38	0	0
T191	0	46	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2762	0	0
T52	45964	54	0	0
T120	0	12	0	0
T127	36792	0	0	0
T128	0	49	0	0
T144	5262	0	0	0
T148	0	46	0	0
T186	0	52	0	0
T187	0	17	0	0
T188	0	15	0	0
T189	0	20	0	0
T190	0	22	0	0
T191	0	37	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2844	0	0
T52	45964	54	0	0
T120	0	5	0	0
T127	36792	0	0	0
T128	0	53	0	0
T144	5262	0	0	0
T148	0	51	0	0
T186	0	35	0	0
T187	0	45	0	0
T188	0	18	0	0
T189	0	32	0	0
T190	0	14	0	0
T191	0	36	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2909	0	0
T52	45964	66	0	0
T120	0	5	0	0
T127	36792	0	0	0
T128	0	52	0	0
T144	5262	0	0	0
T148	0	28	0	0
T186	0	32	0	0
T187	0	55	0	0
T188	0	17	0	0
T189	0	13	0	0
T190	0	40	0	0
T191	0	47	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2738	0	0
T52	45964	65	0	0
T120	0	8	0	0
T127	36792	0	0	0
T128	0	51	0	0
T144	5262	0	0	0
T148	0	51	0	0
T186	0	34	0	0
T187	0	34	0	0
T188	0	17	0	0
T189	0	18	0	0
T190	0	25	0	0
T191	0	49	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2963	0	0
T52	45964	45	0	0
T120	0	18	0	0
T127	36792	0	0	0
T128	0	79	0	0
T144	5262	0	0	0
T148	0	38	0	0
T186	0	45	0	0
T187	0	34	0	0
T188	0	4	0	0
T189	0	16	0	0
T190	0	20	0	0
T191	0	36	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	3662	0	0
T30	8898	0	0	0
T52	45964	54	0	0
T78	0	54	0	0
T127	36792	0	0	0
T128	0	113	0	0
T186	0	25	0	0
T187	0	7	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T199	14930	21	0	0
T200	0	40	0	0
T201	0	4	0	0
T202	0	30	0	0
T203	0	21	0	0
T204	19709	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	3047	0	0
T52	45964	92	0	0
T120	0	22	0	0
T127	36792	0	0	0
T128	0	78	0	0
T144	5262	0	0	0
T148	0	80	0	0
T186	0	45	0	0
T187	0	44	0	0
T188	0	26	0	0
T189	0	38	0	0
T190	0	43	0	0
T191	0	61	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2895	0	0
T52	45964	49	0	0
T120	0	8	0	0
T127	36792	0	0	0
T128	0	48	0	0
T144	5262	0	0	0
T148	0	36	0	0
T186	0	18	0	0
T187	0	41	0	0
T188	0	23	0	0
T189	0	40	0	0
T190	0	48	0	0
T191	0	45	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2690	0	0
T52	45964	61	0	0
T120	0	17	0	0
T127	36792	0	0	0
T128	0	49	0	0
T144	5262	0	0	0
T148	0	8	0	0
T186	0	44	0	0
T187	0	28	0	0
T188	0	6	0	0
T189	0	32	0	0
T190	0	40	0	0
T191	0	34	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2905	0	0
T52	45964	47	0	0
T127	36792	0	0	0
T128	0	79	0	0
T144	5262	0	0	0
T148	0	42	0	0
T186	0	29	0	0
T187	0	23	0	0
T188	0	13	0	0
T189	0	24	0	0
T190	0	49	0	0
T191	0	57	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0
T205	0	3	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2862	0	0
T52	45964	52	0	0
T120	0	13	0	0
T127	36792	0	0	0
T128	0	63	0	0
T144	5262	0	0	0
T148	0	36	0	0
T186	0	60	0	0
T187	0	47	0	0
T188	0	6	0	0
T189	0	19	0	0
T190	0	22	0	0
T191	0	64	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2859	0	0
T52	45964	76	0	0
T120	0	18	0	0
T127	36792	0	0	0
T128	0	66	0	0
T144	5262	0	0	0
T148	0	46	0	0
T186	0	36	0	0
T187	0	27	0	0
T188	0	11	0	0
T189	0	33	0	0
T190	0	26	0	0
T191	0	34	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	3045	0	0
T52	45964	44	0	0
T120	0	22	0	0
T127	36792	0	0	0
T128	0	70	0	0
T144	5262	0	0	0
T148	0	26	0	0
T186	0	35	0	0
T187	0	31	0	0
T188	0	9	0	0
T189	0	23	0	0
T190	0	48	0	0
T191	0	54	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2807	0	0
T52	45964	64	0	0
T120	0	18	0	0
T127	36792	0	0	0
T128	0	87	0	0
T144	5262	0	0	0
T148	0	65	0	0
T186	0	22	0	0
T187	0	35	0	0
T188	0	11	0	0
T189	0	22	0	0
T190	0	32	0	0
T191	0	50	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2942	0	0
T52	45964	55	0	0
T120	0	14	0	0
T127	36792	0	0	0
T128	0	60	0	0
T144	5262	0	0	0
T148	0	66	0	0
T186	0	40	0	0
T187	0	33	0	0
T188	0	11	0	0
T189	0	14	0	0
T190	0	43	0	0
T191	0	64	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2819	0	0
T52	45964	90	0	0
T120	0	14	0	0
T127	36792	0	0	0
T128	0	56	0	0
T144	5262	0	0	0
T148	0	13	0	0
T186	0	25	0	0
T187	0	46	0	0
T188	0	16	0	0
T189	0	36	0	0
T190	0	28	0	0
T191	0	59	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2887	0	0
T52	45964	61	0	0
T120	0	18	0	0
T127	36792	0	0	0
T128	0	98	0	0
T144	5262	0	0	0
T148	0	62	0	0
T186	0	33	0	0
T187	0	71	0	0
T188	0	8	0	0
T189	0	28	0	0
T190	0	47	0	0
T191	0	32	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2930	0	0
T52	45964	70	0	0
T120	0	22	0	0
T127	36792	0	0	0
T128	0	71	0	0
T144	5262	0	0	0
T148	0	44	0	0
T186	0	40	0	0
T187	0	18	0	0
T188	0	28	0	0
T189	0	36	0	0
T190	0	19	0	0
T191	0	78	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	3032	0	0
T52	45964	56	0	0
T127	36792	0	0	0
T128	0	61	0	0
T144	5262	0	0	0
T148	0	39	0	0
T186	0	44	0	0
T187	0	32	0	0
T188	0	26	0	0
T189	0	32	0	0
T190	0	31	0	0
T191	0	58	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0
T206	0	5	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2868	0	0
T52	45964	49	0	0
T120	0	13	0	0
T127	36792	0	0	0
T128	0	45	0	0
T144	5262	0	0	0
T148	0	52	0	0
T186	0	16	0	0
T187	0	26	0	0
T188	0	6	0	0
T189	0	15	0	0
T190	0	40	0	0
T191	0	36	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2798	0	0
T52	45964	35	0	0
T120	0	17	0	0
T127	36792	0	0	0
T128	0	75	0	0
T144	5262	0	0	0
T148	0	66	0	0
T186	0	24	0	0
T187	0	37	0	0
T188	0	3	0	0
T189	0	28	0	0
T190	0	37	0	0
T191	0	47	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2762	0	0
T52	45964	40	0	0
T120	0	15	0	0
T127	36792	0	0	0
T128	0	26	0	0
T144	5262	0	0	0
T148	0	38	0	0
T186	0	31	0	0
T187	0	27	0	0
T188	0	25	0	0
T189	0	20	0	0
T190	0	37	0	0
T191	0	35	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2728	0	0
T52	45964	45	0	0
T120	0	10	0	0
T127	36792	0	0	0
T128	0	109	0	0
T144	5262	0	0	0
T148	0	28	0	0
T186	0	36	0	0
T187	0	28	0	0
T188	0	22	0	0
T189	0	12	0	0
T190	0	11	0	0
T191	0	59	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2768	0	0
T52	45964	41	0	0
T127	36792	0	0	0
T128	0	72	0	0
T144	5262	0	0	0
T148	0	3	0	0
T186	0	19	0	0
T187	0	27	0	0
T188	0	8	0	0
T189	0	15	0	0
T190	0	33	0	0
T191	0	59	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0
T207	0	6	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2879	0	0
T52	45964	67	0	0
T120	0	21	0	0
T127	36792	0	0	0
T128	0	62	0	0
T144	5262	0	0	0
T148	0	24	0	0
T186	0	34	0	0
T187	0	26	0	0
T188	0	33	0	0
T189	0	30	0	0
T190	0	20	0	0
T191	0	64	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2793	0	0
T52	45964	78	0	0
T120	0	10	0	0
T127	36792	0	0	0
T128	0	70	0	0
T144	5262	0	0	0
T148	0	50	0	0
T186	0	20	0	0
T187	0	22	0	0
T188	0	15	0	0
T189	0	27	0	0
T190	0	50	0	0
T191	0	49	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	3055	0	0
T52	45964	73	0	0
T120	0	13	0	0
T127	36792	0	0	0
T128	0	84	0	0
T144	5262	0	0	0
T148	0	43	0	0
T186	0	42	0	0
T187	0	43	0	0
T188	0	13	0	0
T189	0	33	0	0
T190	0	57	0	0
T191	0	50	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24738643	2882	0	0
T52	45964	74	0	0
T120	0	17	0	0
T127	36792	0	0	0
T128	0	76	0	0
T144	5262	0	0	0
T148	0	67	0	0
T186	0	25	0	0
T187	0	30	0	0
T188	0	10	0	0
T189	0	28	0	0
T190	0	31	0	0
T191	0	52	0	0
T192	6683	0	0	0
T193	8230	0	0	0
T194	5138	0	0	0
T195	3881	0	0	0
T196	54636	0	0	0
T197	7627	0	0	0
T198	6484	0	0	0