Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3170526	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

644330

1

T1

145

T2

145

T3

414

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3378092	1			T1	167		T2	705		T3	1469
values[0x0]	216855	1			T1	63		T2	31		T3	138
values[0x1]	219909	1			T1	79		T2	52		T3	142

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2176862	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1637994

1

T1

176

T2

348

T3

827

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11265	1			T1	1		T3	8		T13	3
valid_sources[0x01]	10094	1			T1	1		T3	2		T13	5
valid_sources[0x02]	11876	1			T1	2		T13	2		T14	6
valid_sources[0x03]	10961	1			T3	11		T13	2		T14	5
valid_sources[0x04]	11284	1			T1	3		T13	2		T14	3
valid_sources[0x05]	15270	1			T3	3		T13	2		T16	11
valid_sources[0x06]	10817	1			T3	4		T13	1		T14	2
valid_sources[0x07]	10679	1			T1	1		T13	2		T14	10
valid_sources[0x08]	10700	1			T1	1		T3	19		T13	2
valid_sources[0x09]	10406	1			T1	1		T3	9		T13	1
valid_sources[0x0a]	12655	1			T1	5		T3	15		T13	2
valid_sources[0x0b]	15057	1			T1	1		T3	2		T13	2
valid_sources[0x0c]	10786	1			T1	1		T2	788		T13	4
valid_sources[0x0d]	18948	1			T3	2		T13	1		T14	6
valid_sources[0x0e]	10652	1			T1	1		T13	2		T14	2
valid_sources[0x0f]	10053	1			T1	1		T3	18		T13	1
valid_sources[0x10]	10826	1			T1	1		T3	5		T13	5
valid_sources[0x11]	11161	1			T3	8		T14	5		T18	4
valid_sources[0x12]	11104	1			T1	1		T3	6		T13	3
valid_sources[0x13]	10140	1			T1	1		T3	3		T13	1
valid_sources[0x14]	10625	1			T1	1		T3	2		T13	4
valid_sources[0x15]	10888	1			T1	2		T3	5		T13	1
valid_sources[0x16]	10396	1			T1	1		T14	14		T16	11
valid_sources[0x17]	16909	1			T1	3		T13	2		T14	4
valid_sources[0x18]	11233	1			T3	16		T13	6		T14	8
valid_sources[0x19]	10030	1			T1	2		T3	10		T13	6
valid_sources[0x1a]	11185	1			T1	2		T3	25		T13	3
valid_sources[0x1b]	10315	1			T1	2		T13	1		T14	1
valid_sources[0x1c]	11800	1			T3	2		T13	1		T14	2
valid_sources[0x1d]	10949	1			T1	1		T3	5		T13	5
valid_sources[0x1e]	10181	1			T1	1		T3	25		T13	4
valid_sources[0x1f]	11795	1			T1	4		T3	2		T13	5
valid_sources[0x20]	10285	1			T3	7		T14	3		T17	4
valid_sources[0x21]	11028	1			T1	1		T3	6		T13	1
valid_sources[0x22]	10171	1			T3	12		T13	1		T14	1
valid_sources[0x23]	11218	1			T3	8		T13	3		T14	11
valid_sources[0x24]	39416	1			T1	2		T3	3		T14	3
valid_sources[0x25]	13313	1			T1	3		T13	2		T14	4
valid_sources[0x26]	11915	1			T3	4		T14	11		T15	20
valid_sources[0x27]	12286	1			T1	1		T13	6		T14	2
valid_sources[0x28]	23644	1			T1	1		T3	11		T13	6
valid_sources[0x29]	11470	1			T1	2		T3	15		T13	1
valid_sources[0x2a]	13207	1			T1	1		T3	12		T13	4
valid_sources[0x2b]	13730	1			T3	2		T14	7		T15	14
valid_sources[0x2c]	11468	1			T1	3		T3	6		T14	4
valid_sources[0x2d]	10968	1			T1	6		T14	5		T15	10
valid_sources[0x2e]	18114	1			T1	1		T3	25		T14	3
valid_sources[0x2f]	10684	1			T1	3		T3	20		T13	1
valid_sources[0x30]	14311	1			T1	3		T3	6		T13	1
valid_sources[0x31]	12974	1			T3	2		T13	7		T14	5
valid_sources[0x32]	9942	1			T3	21		T13	6		T14	4
valid_sources[0x33]	11199	1			T3	2		T13	2		T14	2
valid_sources[0x34]	10904	1			T13	1		T14	1		T16	22
valid_sources[0x35]	12128	1			T3	2		T13	3		T14	1
valid_sources[0x36]	28912	1			T3	1		T13	1		T14	9
valid_sources[0x37]	12280	1			T1	3		T3	3		T13	3
valid_sources[0x38]	10269	1			T1	1		T3	5		T13	7
valid_sources[0x39]	12254	1			T1	1		T3	9		T13	6
valid_sources[0x3a]	11113	1			T3	1		T13	1		T14	6
valid_sources[0x3b]	12368	1			T1	1		T3	15		T14	2
valid_sources[0x3c]	10072	1			T13	4		T14	3		T15	3
valid_sources[0x3d]	10035	1			T1	2		T3	1		T13	8
valid_sources[0x3e]	11229	1			T1	3		T13	3		T14	5
valid_sources[0x3f]	22756	1			T1	2		T3	4		T13	7
valid_sources[0x40]	10561	1			T1	2		T13	9		T14	5
valid_sources[0x41]	362970	1			T14	3		T18	6		T19	1
valid_sources[0x42]	10911	1			T1	1		T13	15		T14	8
valid_sources[0x43]	15780	1			T3	13		T13	2		T14	1
valid_sources[0x44]	12381	1			T3	7		T14	1		T15	2
valid_sources[0x45]	10089	1			T1	6		T13	4		T14	8
valid_sources[0x46]	10379	1			T3	13		T13	4		T14	2
valid_sources[0x47]	11221	1			T3	5		T13	4		T14	11
valid_sources[0x48]	13539	1			T1	1		T3	4		T14	6
valid_sources[0x49]	9842	1			T1	1		T13	2		T14	7
valid_sources[0x4a]	11298	1			T1	1		T3	6		T13	2
valid_sources[0x4b]	13400	1			T1	4		T3	2		T13	1
valid_sources[0x4c]	10017	1			T1	3		T14	9		T16	6
valid_sources[0x4d]	10943	1			T1	3		T3	13		T13	1
valid_sources[0x4e]	10373	1			T1	3		T3	16		T13	2
valid_sources[0x4f]	10089	1			T1	1		T3	5		T13	4
valid_sources[0x50]	10770	1			T14	6		T15	6		T16	2
valid_sources[0x51]	13119	1			T1	1		T3	5		T13	3
valid_sources[0x52]	12066	1			T1	1		T3	2		T13	5
valid_sources[0x53]	11438	1			T1	3		T3	14		T13	2
valid_sources[0x54]	9726	1			T1	4		T3	6		T13	4
valid_sources[0x55]	10368	1			T1	1		T13	1		T14	4
valid_sources[0x56]	43419	1			T1	1		T3	9		T14	5
valid_sources[0x57]	10484	1			T3	3		T14	1		T16	4
valid_sources[0x58]	10523	1			T1	1		T13	2		T14	5
valid_sources[0x59]	10755	1			T1	1		T3	5		T13	12
valid_sources[0x5a]	10455	1			T1	2		T3	7		T13	6
valid_sources[0x5b]	12854	1			T1	1		T13	5		T14	4
valid_sources[0x5c]	10453	1			T1	2		T3	13		T14	3
valid_sources[0x5d]	11825	1			T3	2		T13	1		T15	10
valid_sources[0x5e]	13013	1			T1	2		T14	7		T18	7
valid_sources[0x5f]	10654	1			T1	1		T3	2		T14	5
valid_sources[0x60]	29002	1			T1	2		T3	4		T13	1
valid_sources[0x61]	13358	1			T1	1		T3	4		T13	4
valid_sources[0x62]	10080	1			T1	1		T3	5		T13	4
valid_sources[0x63]	10504	1			T1	1		T3	1		T13	4
valid_sources[0x64]	12362	1			T1	2		T3	7		T13	4
valid_sources[0x65]	10462	1			T3	6		T13	5		T14	2
valid_sources[0x66]	47422	1			T1	1		T3	13		T13	1
valid_sources[0x67]	9924	1			T1	2		T3	3		T13	1
valid_sources[0x68]	9964	1			T1	1		T13	1		T14	8
valid_sources[0x69]	40100	1			T1	3		T3	28		T13	2
valid_sources[0x6a]	12269	1			T1	3		T3	4		T13	1
valid_sources[0x6b]	11204	1			T1	1		T3	12		T13	1
valid_sources[0x6c]	23336	1			T3	5		T14	1		T15	20
valid_sources[0x6d]	10037	1			T3	12		T14	3		T15	11
valid_sources[0x6e]	13453	1			T1	1		T3	11		T13	6
valid_sources[0x6f]	11141	1			T1	2		T3	9		T13	2
valid_sources[0x70]	10126	1			T1	5		T3	18		T14	5
valid_sources[0x71]	16253	1			T3	1		T13	2		T14	1
valid_sources[0x72]	10673	1			T3	11		T13	2		T14	1
valid_sources[0x73]	10471	1			T1	1		T3	6		T14	5
valid_sources[0x74]	10223	1			T3	1		T14	10		T16	7
valid_sources[0x75]	11067	1			T3	1		T13	2		T15	2
valid_sources[0x76]	12252	1			T1	2		T3	15		T13	1
valid_sources[0x77]	10282	1			T3	5		T13	9		T14	11
valid_sources[0x78]	12151	1			T1	2		T3	8		T13	1
valid_sources[0x79]	11914	1			T3	18		T14	2		T15	5
valid_sources[0x7a]	14318	1			T1	2		T3	12		T14	2
valid_sources[0x7b]	48062	1			T1	1		T14	5		T15	1
valid_sources[0x7c]	10111	1			T1	4		T13	1		T14	10
valid_sources[0x7d]	10449	1			T1	2		T3	21		T14	2
valid_sources[0x7e]	11446	1			T3	5		T13	2		T14	6
valid_sources[0x7f]	10092	1			T1	1		T3	1		T14	1
valid_sources[0x80]	15824	1			T1	3		T3	9		T13	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

347661

1

T1

60

T2

123

T3

263

values[0x0]

all_enables

biggest_size

156092

1

T1

42

T2

9

T3

84

values[0x1]

all_enables

biggest_size

140577

1

T1

43

T2

13

T3

67