Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23795106	15477	0	0
attest_sw_binding_0_rd_A	23795106	3004	0	0
attest_sw_binding_1_rd_A	23795106	2919	0	0
attest_sw_binding_2_rd_A	23795106	3129	0	0
attest_sw_binding_3_rd_A	23795106	3210	0	0
attest_sw_binding_4_rd_A	23795106	3029	0	0
attest_sw_binding_5_rd_A	23795106	3094	0	0
attest_sw_binding_6_rd_A	23795106	3168	0	0
attest_sw_binding_7_rd_A	23795106	3171	0	0
intr_enable_rd_A	23795106	3683	0	0
key_version_rd_A	23795106	3144	0	0
max_creator_key_ver_regwen_rd_A	23795106	2929	0	0
max_owner_int_key_ver_regwen_rd_A	23795106	3048	0	0
max_owner_key_ver_regwen_rd_A	23795106	2948	0	0
reseed_interval_regwen_rd_A	23795106	3142	0	0
salt_0_rd_A	23795106	2954	0	0
salt_1_rd_A	23795106	3155	0	0
salt_2_rd_A	23795106	3042	0	0
salt_3_rd_A	23795106	3086	0	0
salt_4_rd_A	23795106	3017	0	0
salt_5_rd_A	23795106	3111	0	0
salt_6_rd_A	23795106	3112	0	0
salt_7_rd_A	23795106	3044	0	0
sealing_sw_binding_0_rd_A	23795106	3070	0	0
sealing_sw_binding_1_rd_A	23795106	3103	0	0
sealing_sw_binding_2_rd_A	23795106	3047	0	0
sealing_sw_binding_3_rd_A	23795106	3068	0	0
sealing_sw_binding_4_rd_A	23795106	2969	0	0
sealing_sw_binding_5_rd_A	23795106	3167	0	0
sealing_sw_binding_6_rd_A	23795106	3016	0	0
sealing_sw_binding_7_rd_A	23795106	3014	0	0
sideload_clear_rd_A	23795106	3213	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	15477	0	0
T38	8572	0	0	0
T46	0	317	0	0
T51	0	91	0	0
T54	21084	56	0	0
T55	0	582	0	0
T68	4023	0	0	0
T71	0	157	0	0
T72	0	31	0	0
T80	0	366	0	0
T117	0	124	0	0
T118	16571	0	0	0
T119	6174	0	0	0
T120	32368	0	0	0
T121	5679	0	0	0
T122	9070	0	0	0
T123	3565	0	0	0
T124	160745	0	0	0
T126	0	1300	0	0
T127	0	20	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3004	0	0
T11	81559	0	0	0
T67	0	56	0	0
T92	7954	0	0	0
T127	24933	14	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	26	0	0
T183	0	22	0	0
T184	0	68	0	0
T185	0	26	0	0
T186	0	24	0	0
T187	0	19	0	0
T188	0	68	0	0
T189	0	64	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	2919	0	0
T11	81559	0	0	0
T67	0	52	0	0
T92	7954	0	0	0
T127	24933	35	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	28	0	0
T183	0	18	0	0
T184	0	52	0	0
T185	0	50	0	0
T186	0	51	0	0
T187	0	27	0	0
T188	0	42	0	0
T189	0	56	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3129	0	0
T11	81559	0	0	0
T67	0	54	0	0
T92	7954	0	0	0
T127	24933	21	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	28	0	0
T183	0	29	0	0
T184	0	76	0	0
T185	0	37	0	0
T186	0	47	0	0
T187	0	33	0	0
T188	0	63	0	0
T189	0	56	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3210	0	0
T11	81559	0	0	0
T67	0	56	0	0
T92	7954	0	0	0
T127	24933	35	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	20	0	0
T183	0	19	0	0
T184	0	97	0	0
T185	0	31	0	0
T186	0	37	0	0
T187	0	50	0	0
T188	0	63	0	0
T189	0	49	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3029	0	0
T11	81559	0	0	0
T67	0	65	0	0
T92	7954	0	0	0
T127	24933	23	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	7	0	0
T183	0	39	0	0
T184	0	70	0	0
T185	0	33	0	0
T186	0	16	0	0
T187	0	17	0	0
T188	0	54	0	0
T189	0	35	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3094	0	0
T11	81559	0	0	0
T67	0	54	0	0
T92	7954	0	0	0
T127	24933	40	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	18	0	0
T183	0	27	0	0
T184	0	56	0	0
T185	0	43	0	0
T186	0	19	0	0
T187	0	38	0	0
T188	0	57	0	0
T189	0	67	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3168	0	0
T11	81559	0	0	0
T67	0	55	0	0
T92	7954	0	0	0
T127	24933	28	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	13	0	0
T183	0	11	0	0
T184	0	86	0	0
T185	0	12	0	0
T186	0	26	0	0
T187	0	36	0	0
T188	0	81	0	0
T189	0	59	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3171	0	0
T11	81559	0	0	0
T67	0	71	0	0
T92	7954	0	0	0
T127	24933	18	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	30	0	0
T183	0	23	0	0
T184	0	70	0	0
T185	0	57	0	0
T186	0	30	0	0
T187	0	38	0	0
T188	0	87	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0
T195	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3683	0	0
T41	15081	0	0	0
T67	0	53	0	0
T81	354212	79	0	0
T127	0	16	0	0
T182	0	22	0	0
T183	0	65	0	0
T184	0	53	0	0
T196	0	6	0	0
T197	0	17	0	0
T198	0	19	0	0
T199	0	5	0	0
T200	5341	0	0	0
T201	10172	0	0	0
T202	96870	0	0	0
T203	986	0	0	0
T204	1631	0	0	0
T205	23646	0	0	0
T206	4527	0	0	0
T207	5294	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3144	0	0
T11	81559	0	0	0
T67	0	50	0	0
T92	7954	0	0	0
T127	24933	33	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	29	0	0
T183	0	43	0	0
T184	0	46	0	0
T185	0	44	0	0
T186	0	22	0	0
T187	0	34	0	0
T188	0	57	0	0
T189	0	38	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	2929	0	0
T11	81559	0	0	0
T67	0	44	0	0
T92	7954	0	0	0
T127	24933	27	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	22	0	0
T183	0	14	0	0
T184	0	65	0	0
T185	0	33	0	0
T186	0	32	0	0
T187	0	29	0	0
T188	0	65	0	0
T189	0	41	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3048	0	0
T11	81559	0	0	0
T67	0	41	0	0
T92	7954	0	0	0
T127	24933	23	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	22	0	0
T183	0	42	0	0
T184	0	49	0	0
T185	0	48	0	0
T186	0	22	0	0
T187	0	32	0	0
T188	0	54	0	0
T189	0	56	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	2948	0	0
T11	81559	0	0	0
T67	0	64	0	0
T92	7954	0	0	0
T127	24933	40	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	12	0	0
T183	0	29	0	0
T184	0	62	0	0
T185	0	37	0	0
T186	0	29	0	0
T187	0	17	0	0
T188	0	72	0	0
T189	0	44	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3142	0	0
T11	81559	0	0	0
T67	0	66	0	0
T92	7954	0	0	0
T127	24933	26	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	18	0	0
T183	0	35	0	0
T184	0	81	0	0
T185	0	33	0	0
T186	0	29	0	0
T187	0	17	0	0
T188	0	89	0	0
T189	0	50	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	2954	0	0
T11	81559	0	0	0
T67	0	66	0	0
T92	7954	0	0	0
T127	24933	45	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	17	0	0
T183	0	30	0	0
T184	0	62	0	0
T185	0	50	0	0
T186	0	20	0	0
T187	0	29	0	0
T188	0	34	0	0
T189	0	46	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3155	0	0
T11	81559	0	0	0
T67	0	79	0	0
T92	7954	0	0	0
T127	24933	28	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	22	0	0
T183	0	29	0	0
T184	0	54	0	0
T185	0	51	0	0
T186	0	26	0	0
T187	0	42	0	0
T188	0	85	0	0
T189	0	61	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3042	0	0
T11	81559	0	0	0
T67	0	73	0	0
T92	7954	0	0	0
T127	24933	17	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	18	0	0
T183	0	22	0	0
T184	0	48	0	0
T185	0	20	0	0
T186	0	37	0	0
T187	0	19	0	0
T188	0	81	0	0
T189	0	61	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3086	0	0
T11	81559	0	0	0
T67	0	71	0	0
T92	7954	0	0	0
T127	24933	26	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	26	0	0
T183	0	41	0	0
T184	0	64	0	0
T185	0	35	0	0
T186	0	27	0	0
T187	0	36	0	0
T188	0	50	0	0
T189	0	43	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3017	0	0
T11	81559	0	0	0
T67	0	64	0	0
T92	7954	0	0	0
T127	24933	16	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	15	0	0
T183	0	45	0	0
T184	0	63	0	0
T185	0	22	0	0
T186	0	48	0	0
T187	0	43	0	0
T188	0	67	0	0
T189	0	83	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3111	0	0
T11	81559	0	0	0
T67	0	50	0	0
T92	7954	0	0	0
T127	24933	43	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	29	0	0
T183	0	15	0	0
T184	0	65	0	0
T185	0	28	0	0
T186	0	29	0	0
T187	0	48	0	0
T188	0	34	0	0
T189	0	63	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3112	0	0
T11	81559	0	0	0
T67	0	38	0	0
T92	7954	0	0	0
T127	24933	2	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	10	0	0
T183	0	36	0	0
T184	0	62	0	0
T185	0	29	0	0
T186	0	18	0	0
T187	0	42	0	0
T188	0	66	0	0
T189	0	55	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3044	0	0
T11	81559	0	0	0
T67	0	76	0	0
T92	7954	0	0	0
T127	24933	30	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	19	0	0
T183	0	24	0	0
T184	0	78	0	0
T185	0	28	0	0
T186	0	31	0	0
T187	0	32	0	0
T188	0	86	0	0
T189	0	42	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3070	0	0
T11	81559	0	0	0
T67	0	50	0	0
T92	7954	0	0	0
T127	24933	25	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	25	0	0
T183	0	12	0	0
T184	0	75	0	0
T185	0	20	0	0
T186	0	21	0	0
T187	0	26	0	0
T188	0	49	0	0
T189	0	66	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3103	0	0
T11	81559	0	0	0
T67	0	37	0	0
T92	7954	0	0	0
T127	24933	31	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	37	0	0
T183	0	18	0	0
T184	0	41	0	0
T185	0	52	0	0
T186	0	37	0	0
T187	0	34	0	0
T188	0	65	0	0
T189	0	51	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3047	0	0
T11	81559	0	0	0
T67	0	41	0	0
T92	7954	0	0	0
T127	24933	17	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	27	0	0
T183	0	49	0	0
T184	0	85	0	0
T185	0	14	0	0
T186	0	31	0	0
T187	0	30	0	0
T188	0	49	0	0
T189	0	51	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3068	0	0
T11	81559	0	0	0
T67	0	64	0	0
T92	7954	0	0	0
T127	24933	14	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	38	0	0
T183	0	31	0	0
T184	0	75	0	0
T185	0	20	0	0
T186	0	30	0	0
T187	0	18	0	0
T188	0	65	0	0
T189	0	59	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	2969	0	0
T11	81559	0	0	0
T67	0	73	0	0
T92	7954	0	0	0
T127	24933	20	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	14	0	0
T183	0	20	0	0
T184	0	49	0	0
T185	0	51	0	0
T186	0	33	0	0
T187	0	36	0	0
T188	0	36	0	0
T189	0	43	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3167	0	0
T11	81559	0	0	0
T67	0	71	0	0
T92	7954	0	0	0
T127	24933	17	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	27	0	0
T183	0	23	0	0
T184	0	71	0	0
T185	0	16	0	0
T186	0	52	0	0
T187	0	36	0	0
T188	0	53	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0
T208	0	1	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3016	0	0
T11	81559	0	0	0
T67	0	53	0	0
T92	7954	0	0	0
T127	24933	24	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	22	0	0
T183	0	5	0	0
T184	0	87	0	0
T185	0	40	0	0
T186	0	40	0	0
T187	0	48	0	0
T188	0	65	0	0
T189	0	29	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3014	0	0
T11	81559	0	0	0
T67	0	64	0	0
T92	7954	0	0	0
T127	24933	41	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	18	0	0
T183	0	23	0	0
T184	0	45	0	0
T185	0	52	0	0
T186	0	36	0	0
T187	0	24	0	0
T188	0	82	0	0
T189	0	67	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23795106	3213	0	0
T11	81559	0	0	0
T67	0	42	0	0
T92	7954	0	0	0
T127	24933	28	0	0
T177	6406	0	0	0
T178	6984	0	0	0
T182	0	21	0	0
T183	0	37	0	0
T184	0	54	0	0
T185	0	31	0	0
T186	0	26	0	0
T187	0	68	0	0
T188	0	81	0	0
T189	0	54	0	0
T190	9601	0	0	0
T191	3309	0	0	0
T192	5624	0	0	0
T193	102526	0	0	0
T194	4458	0	0	0