Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3275930	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

632840

1

T1

328

T2

88

T3

5650

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3481653	1			T1	952		T2	12896		T3	9274
values[0x0]	212082	1			T1	111		T2	12		T3	1992
values[0x1]	215035	1			T1	131		T2	19		T3	2045

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2243373	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1665397

1

T1

564

T2

4331

T3

7620

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14578	1			T1	7		T2	59		T13	3
valid_sources[0x01]	11234	1			T1	7		T2	48		T13	1
valid_sources[0x02]	10427	1			T1	7		T2	51		T13	1
valid_sources[0x03]	12628	1			T1	5		T2	39		T14	16
valid_sources[0x04]	10164	1			T1	4		T2	52		T14	13
valid_sources[0x05]	11090	1			T1	6		T2	44		T13	4
valid_sources[0x06]	10515	1			T1	6		T2	62		T13	3
valid_sources[0x07]	11863	1			T1	4		T2	66		T13	1
valid_sources[0x08]	10520	1			T1	1		T2	69		T13	1
valid_sources[0x09]	10174	1			T1	5		T2	67		T13	2
valid_sources[0x0a]	29483	1			T1	2		T2	48		T13	1
valid_sources[0x0b]	10099	1			T1	3		T2	38		T13	1
valid_sources[0x0c]	12158	1			T1	1		T2	53		T13	3
valid_sources[0x0d]	10801	1			T1	4		T2	44		T13	2
valid_sources[0x0e]	9939	1			T1	5		T2	40		T13	4
valid_sources[0x0f]	10349	1			T1	5		T2	47		T13	2
valid_sources[0x10]	10968	1			T1	2		T2	54		T13	1
valid_sources[0x11]	19507	1			T1	5		T2	60		T13	3
valid_sources[0x12]	10435	1			T1	8		T2	47		T13	2
valid_sources[0x13]	10942	1			T1	4		T2	53		T13	1
valid_sources[0x14]	10414	1			T1	6		T2	33		T13	1
valid_sources[0x15]	15809	1			T1	5		T2	61		T13	4
valid_sources[0x16]	345495	1			T1	1		T2	42		T13	1
valid_sources[0x17]	39371	1			T1	3		T2	46		T3	13311
valid_sources[0x18]	10283	1			T1	5		T2	50		T13	7
valid_sources[0x19]	14773	1			T1	5		T2	64		T16	4
valid_sources[0x1a]	11727	1			T1	6		T2	50		T13	2
valid_sources[0x1b]	10353	1			T1	4		T2	54		T13	2
valid_sources[0x1c]	11044	1			T1	13		T2	47		T13	2
valid_sources[0x1d]	9808	1			T1	9		T2	59		T13	1
valid_sources[0x1e]	10040	1			T1	5		T2	48		T17	6
valid_sources[0x1f]	13562	1			T1	2		T2	48		T13	6
valid_sources[0x20]	14733	1			T1	1		T2	47		T16	5
valid_sources[0x21]	14671	1			T1	3		T2	54		T13	2
valid_sources[0x22]	26356	1			T1	3		T2	52		T13	1
valid_sources[0x23]	28555	1			T1	4		T2	49		T13	1
valid_sources[0x24]	10623	1			T1	7		T2	60		T13	3
valid_sources[0x25]	10297	1			T1	3		T2	70		T13	5
valid_sources[0x26]	10136	1			T1	1		T2	44		T13	4
valid_sources[0x27]	10879	1			T1	4		T2	31		T13	2
valid_sources[0x28]	12930	1			T1	10		T2	52		T13	3
valid_sources[0x29]	10055	1			T1	4		T2	38		T13	1
valid_sources[0x2a]	11982	1			T1	3		T2	48		T17	2
valid_sources[0x2b]	9824	1			T1	5		T2	52		T13	5
valid_sources[0x2c]	13166	1			T1	8		T2	49		T13	3
valid_sources[0x2d]	16481	1			T1	8		T2	47		T13	4
valid_sources[0x2e]	13560	1			T1	6		T2	48		T13	2
valid_sources[0x2f]	10731	1			T1	4		T2	45		T13	3
valid_sources[0x30]	15026	1			T1	1		T2	58		T13	2
valid_sources[0x31]	12566	1			T1	4		T2	49		T13	1
valid_sources[0x32]	9644	1			T1	1		T2	40		T13	3
valid_sources[0x33]	11407	1			T1	5		T2	35		T16	3
valid_sources[0x34]	10015	1			T1	3		T2	61		T13	4
valid_sources[0x35]	20443	1			T1	2		T2	55		T13	1
valid_sources[0x36]	10187	1			T1	3		T2	51		T13	1
valid_sources[0x37]	12409	1			T1	4		T2	52		T13	7
valid_sources[0x38]	13056	1			T1	2		T2	53		T13	5
valid_sources[0x39]	10385	1			T1	6		T2	63		T14	5
valid_sources[0x3a]	10444	1			T1	2		T2	54		T13	5
valid_sources[0x3b]	11679	1			T1	6		T2	41		T13	3
valid_sources[0x3c]	9990	1			T1	6		T2	72		T13	2
valid_sources[0x3d]	10510	1			T1	1		T2	43		T13	2
valid_sources[0x3e]	10305	1			T1	6		T2	35		T13	1
valid_sources[0x3f]	11135	1			T1	2		T2	41		T13	7
valid_sources[0x40]	10000	1			T1	4		T2	61		T13	4
valid_sources[0x41]	10487	1			T1	4		T2	56		T13	2
valid_sources[0x42]	9848	1			T1	4		T2	52		T13	6
valid_sources[0x43]	12932	1			T1	6		T2	39		T19	7
valid_sources[0x44]	13625	1			T1	9		T2	55		T13	3
valid_sources[0x45]	11317	1			T1	3		T2	50		T13	1
valid_sources[0x46]	12656	1			T1	9		T2	53		T13	2
valid_sources[0x47]	10745	1			T1	5		T2	40		T13	2
valid_sources[0x48]	10494	1			T1	7		T2	50		T13	5
valid_sources[0x49]	10465	1			T1	3		T2	55		T13	2
valid_sources[0x4a]	10906	1			T1	3		T2	60		T16	2
valid_sources[0x4b]	10950	1			T1	11		T2	63		T14	5
valid_sources[0x4c]	25922	1			T1	3		T2	48		T13	1
valid_sources[0x4d]	10998	1			T1	3		T2	60		T13	3
valid_sources[0x4e]	12318	1			T1	4		T2	49		T13	2
valid_sources[0x4f]	12732	1			T1	11		T2	54		T13	1
valid_sources[0x50]	11401	1			T1	3		T2	46		T13	1
valid_sources[0x51]	10293	1			T1	1		T2	38		T13	3
valid_sources[0x52]	10750	1			T1	1		T2	62		T13	3
valid_sources[0x53]	10958	1			T1	9		T2	54		T13	2
valid_sources[0x54]	10167	1			T1	7		T2	61		T13	1
valid_sources[0x55]	10196	1			T1	1		T2	48		T13	2
valid_sources[0x56]	10516	1			T1	2		T2	48		T13	4
valid_sources[0x57]	11140	1			T1	4		T2	43		T13	1
valid_sources[0x58]	9945	1			T1	4		T2	55		T13	3
valid_sources[0x59]	13944	1			T1	9		T2	49		T13	1
valid_sources[0x5a]	11918	1			T1	5		T2	55		T13	1
valid_sources[0x5b]	10426	1			T1	5		T2	42		T13	5
valid_sources[0x5c]	13722	1			T1	1		T2	48		T13	3
valid_sources[0x5d]	10235	1			T1	7		T2	60		T13	2
valid_sources[0x5e]	10555	1			T1	2		T2	43		T13	3
valid_sources[0x5f]	11951	1			T1	1		T2	40		T16	8
valid_sources[0x60]	10708	1			T1	2		T2	49		T13	5
valid_sources[0x61]	9889	1			T1	4		T2	42		T13	2
valid_sources[0x62]	10036	1			T1	5		T2	67		T13	3
valid_sources[0x63]	11235	1			T1	4		T2	54		T13	1
valid_sources[0x64]	9935	1			T1	1		T2	38		T13	2
valid_sources[0x65]	23515	1			T1	7		T2	54		T13	1
valid_sources[0x66]	10715	1			T1	3		T2	47		T13	4
valid_sources[0x67]	10405	1			T1	2		T2	55		T13	3
valid_sources[0x68]	10654	1			T1	6		T2	58		T13	5
valid_sources[0x69]	15382	1			T1	13		T2	67		T16	4
valid_sources[0x6a]	12343	1			T1	3		T2	49		T13	1
valid_sources[0x6b]	12375	1			T1	2		T2	45		T13	1
valid_sources[0x6c]	13238	1			T1	2		T2	68		T13	2
valid_sources[0x6d]	17621	1			T1	7		T2	44		T13	3
valid_sources[0x6e]	10664	1			T1	2		T2	61		T13	2
valid_sources[0x6f]	11869	1			T1	5		T2	46		T13	1
valid_sources[0x70]	10626	1			T1	1		T2	57		T13	1
valid_sources[0x71]	12624	1			T1	1		T2	55		T13	2
valid_sources[0x72]	10373	1			T1	5		T2	56		T13	2
valid_sources[0x73]	12106	1			T1	3		T2	36		T13	3
valid_sources[0x74]	11062	1			T1	4		T2	47		T13	1
valid_sources[0x75]	11054	1			T1	6		T2	64		T13	2
valid_sources[0x76]	12341	1			T1	7		T2	39		T16	2
valid_sources[0x77]	10300	1			T1	7		T2	41		T13	3
valid_sources[0x78]	13426	1			T1	6		T2	45		T13	1
valid_sources[0x79]	11569	1			T2	55		T13	3		T14	1
valid_sources[0x7a]	9950	1			T1	10		T2	42		T13	4
valid_sources[0x7b]	10904	1			T1	6		T2	49		T13	5
valid_sources[0x7c]	9793	1			T1	3		T2	55		T13	5
valid_sources[0x7d]	10520	1			T1	5		T2	53		T13	2
valid_sources[0x7e]	11777	1			T1	1		T2	47		T13	5
valid_sources[0x7f]	11019	1			T1	1		T2	40		T13	1
valid_sources[0x80]	9931	1			T1	4		T2	33		T13	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

341072

1

T1

182

T2

81

T3

3052

values[0x0]

all_enables

biggest_size

153365

1

T1

75

T2

5

T3

1337

values[0x1]

all_enables

biggest_size

138403

1

T1

71

T2

2

T3

1261