Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
21742998 |
21580788 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21742998 |
21580788 |
0 |
0 |
T1 |
4148 |
4078 |
0 |
0 |
T2 |
60637 |
60566 |
0 |
0 |
T3 |
130432 |
128988 |
0 |
0 |
T13 |
6932 |
6779 |
0 |
0 |
T14 |
5419 |
5265 |
0 |
0 |
T15 |
12589 |
12491 |
0 |
0 |
T16 |
7904 |
7837 |
0 |
0 |
T17 |
10302 |
10232 |
0 |
0 |
T18 |
9081 |
8998 |
0 |
0 |
T19 |
6715 |
6625 |
0 |
0 |