Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23487217	20863	0	0
attest_sw_binding_0_rd_A	23487217	3612	0	0
attest_sw_binding_1_rd_A	23487217	3580	0	0
attest_sw_binding_2_rd_A	23487217	3708	0	0
attest_sw_binding_3_rd_A	23487217	3622	0	0
attest_sw_binding_4_rd_A	23487217	3563	0	0
attest_sw_binding_5_rd_A	23487217	3639	0	0
attest_sw_binding_6_rd_A	23487217	3463	0	0
attest_sw_binding_7_rd_A	23487217	3689	0	0
intr_enable_rd_A	23487217	3878	0	0
key_version_rd_A	23487217	3733	0	0
max_creator_key_ver_regwen_rd_A	23487217	3407	0	0
max_owner_int_key_ver_regwen_rd_A	23487217	3597	0	0
max_owner_key_ver_regwen_rd_A	23487217	3492	0	0
reseed_interval_regwen_rd_A	23487217	3711	0	0
salt_0_rd_A	23487217	3694	0	0
salt_1_rd_A	23487217	3527	0	0
salt_2_rd_A	23487217	3713	0	0
salt_3_rd_A	23487217	3599	0	0
salt_4_rd_A	23487217	3616	0	0
salt_5_rd_A	23487217	3835	0	0
salt_6_rd_A	23487217	3650	0	0
salt_7_rd_A	23487217	3603	0	0
sealing_sw_binding_0_rd_A	23487217	3561	0	0
sealing_sw_binding_1_rd_A	23487217	3679	0	0
sealing_sw_binding_2_rd_A	23487217	3534	0	0
sealing_sw_binding_3_rd_A	23487217	3621	0	0
sealing_sw_binding_4_rd_A	23487217	3648	0	0
sealing_sw_binding_5_rd_A	23487217	3611	0	0
sealing_sw_binding_6_rd_A	23487217	3485	0	0
sealing_sw_binding_7_rd_A	23487217	3517	0	0
sideload_clear_rd_A	23487217	3578	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	20863	0	0
T35	9978	0	0	0
T36	3920	0	0	0
T44	30252	49	0	0
T47	6089	0	0	0
T51	5373	0	0	0
T53	0	527	0	0
T63	0	488	0	0
T64	0	224	0	0
T100	24144	0	0	0
T111	0	410	0	0
T123	0	1062	0	0
T124	0	685	0	0
T125	0	2407	0	0
T126	0	191	0	0
T127	0	291	0	0
T128	7264	0	0	0
T129	5639	0	0	0
T130	27611	0	0	0
T131	82180	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3612	0	0
T140	0	48	0	0
T149	0	36	0	0
T155	0	171	0	0
T157	0	42	0	0
T176	70455	59	0	0
T177	0	26	0	0
T178	0	6	0	0
T179	0	7	0	0
T180	0	233	0	0
T181	0	1	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3580	0	0
T140	0	27	0	0
T149	0	48	0	0
T155	0	117	0	0
T157	0	28	0	0
T176	70455	66	0	0
T177	0	40	0	0
T178	0	14	0	0
T179	0	5	0	0
T180	0	229	0	0
T181	0	5	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3708	0	0
T140	0	21	0	0
T149	0	36	0	0
T155	0	122	0	0
T176	0	56	0	0
T177	0	29	0	0
T178	0	13	0	0
T179	0	14	0	0
T180	0	224	0	0
T181	0	8	0	0
T191	7226	6	0	0
T192	5240	0	0	0
T193	15481	0	0	0
T194	19112	0	0	0
T195	5588	0	0	0
T196	7192	0	0	0
T197	10114	0	0	0
T198	44966	0	0	0
T199	3666	0	0	0
T200	1053	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3622	0	0
T140	0	29	0	0
T149	0	34	0	0
T155	0	74	0	0
T157	0	46	0	0
T176	70455	64	0	0
T177	0	21	0	0
T178	0	4	0	0
T179	0	16	0	0
T180	0	227	0	0
T181	0	10	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3563	0	0
T140	0	12	0	0
T149	0	27	0	0
T155	0	132	0	0
T157	0	28	0	0
T176	70455	44	0	0
T177	0	43	0	0
T178	0	18	0	0
T180	0	243	0	0
T181	0	6	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0
T201	0	2	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3639	0	0
T140	0	88	0	0
T149	0	36	0	0
T155	0	138	0	0
T157	0	35	0	0
T176	70455	51	0	0
T177	0	28	0	0
T178	0	23	0	0
T179	0	16	0	0
T180	0	216	0	0
T181	0	5	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3463	0	0
T122	0	30	0	0
T140	0	19	0	0
T149	0	58	0	0
T155	0	143	0	0
T157	0	32	0	0
T176	70455	69	0	0
T177	0	23	0	0
T178	0	4	0	0
T180	0	205	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0
T201	0	9	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3689	0	0
T140	0	39	0	0
T149	0	21	0	0
T155	0	115	0	0
T157	0	38	0	0
T176	70455	61	0	0
T177	0	55	0	0
T178	0	17	0	0
T180	0	229	0	0
T181	0	20	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0
T201	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3878	0	0
T89	22704	0	0	0
T176	0	97	0	0
T177	0	11	0	0
T202	538111	72	0	0
T203	0	21	0	0
T204	0	21	0	0
T205	0	8	0	0
T206	0	21	0	0
T207	0	27	0	0
T208	0	21	0	0
T209	0	13	0	0
T210	6235	0	0	0
T211	26357	0	0	0
T212	6079	0	0	0
T213	40830	0	0	0
T214	9378	0	0	0
T215	61911	0	0	0
T216	2401	0	0	0
T217	6482	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3733	0	0
T140	0	60	0	0
T149	0	43	0	0
T155	0	131	0	0
T157	0	43	0	0
T176	70455	50	0	0
T177	0	48	0	0
T178	0	9	0	0
T179	0	2	0	0
T180	0	207	0	0
T181	0	8	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3407	0	0
T140	0	16	0	0
T149	0	59	0	0
T155	0	78	0	0
T157	0	35	0	0
T176	70455	61	0	0
T177	0	28	0	0
T178	0	14	0	0
T180	0	220	0	0
T181	0	3	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0
T201	0	3	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3597	0	0
T140	0	32	0	0
T149	0	34	0	0
T155	0	101	0	0
T157	0	27	0	0
T176	70455	57	0	0
T177	0	23	0	0
T178	0	13	0	0
T179	0	7	0	0
T180	0	221	0	0
T181	0	7	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3492	0	0
T140	0	58	0	0
T149	0	32	0	0
T155	0	127	0	0
T157	0	45	0	0
T176	70455	73	0	0
T177	0	32	0	0
T178	0	7	0	0
T179	0	2	0	0
T180	0	228	0	0
T181	0	6	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3711	0	0
T140	0	50	0	0
T149	0	26	0	0
T155	0	154	0	0
T157	0	47	0	0
T176	70455	73	0	0
T177	0	30	0	0
T178	0	23	0	0
T179	0	8	0	0
T180	0	235	0	0
T181	0	10	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3694	0	0
T140	0	75	0	0
T149	0	33	0	0
T155	0	111	0	0
T157	0	44	0	0
T176	70455	56	0	0
T177	0	41	0	0
T178	0	18	0	0
T180	0	215	0	0
T181	0	12	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0
T201	0	5	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3527	0	0
T140	0	22	0	0
T149	0	46	0	0
T155	0	124	0	0
T157	0	50	0	0
T176	70455	71	0	0
T177	0	25	0	0
T178	0	14	0	0
T180	0	262	0	0
T181	0	11	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0
T201	0	15	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3713	0	0
T140	0	41	0	0
T149	0	38	0	0
T155	0	117	0	0
T157	0	41	0	0
T176	70455	67	0	0
T177	0	45	0	0
T178	0	19	0	0
T179	0	16	0	0
T180	0	226	0	0
T181	0	2	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3599	0	0
T140	0	44	0	0
T149	0	57	0	0
T155	0	157	0	0
T157	0	41	0	0
T176	70455	68	0	0
T177	0	20	0	0
T178	0	8	0	0
T179	0	16	0	0
T180	0	234	0	0
T181	0	4	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3616	0	0
T140	0	42	0	0
T149	0	51	0	0
T155	0	106	0	0
T157	0	28	0	0
T176	70455	33	0	0
T177	0	25	0	0
T178	0	20	0	0
T180	0	254	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0
T201	0	13	0	0
T218	0	4	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3835	0	0
T140	0	59	0	0
T149	0	51	0	0
T155	0	140	0	0
T157	0	59	0	0
T176	70455	83	0	0
T177	0	14	0	0
T178	0	9	0	0
T179	0	6	0	0
T180	0	251	0	0
T181	0	19	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3650	0	0
T140	0	49	0	0
T149	0	39	0	0
T155	0	119	0	0
T157	0	50	0	0
T176	70455	25	0	0
T177	0	41	0	0
T178	0	19	0	0
T180	0	241	0	0
T181	0	3	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0
T201	0	14	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3603	0	0
T140	0	65	0	0
T149	0	27	0	0
T155	0	160	0	0
T157	0	47	0	0
T176	70455	65	0	0
T177	0	25	0	0
T178	0	8	0	0
T179	0	1	0	0
T180	0	225	0	0
T181	0	15	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3561	0	0
T140	0	44	0	0
T149	0	35	0	0
T155	0	111	0	0
T157	0	37	0	0
T176	70455	25	0	0
T177	0	29	0	0
T178	0	15	0	0
T179	0	7	0	0
T180	0	218	0	0
T181	0	11	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3679	0	0
T140	0	66	0	0
T149	0	43	0	0
T155	0	122	0	0
T157	0	53	0	0
T176	70455	62	0	0
T177	0	57	0	0
T178	0	14	0	0
T179	0	2	0	0
T180	0	221	0	0
T181	0	4	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3534	0	0
T140	0	31	0	0
T149	0	46	0	0
T155	0	108	0	0
T176	70455	34	0	0
T177	0	21	0	0
T178	0	19	0	0
T179	0	5	0	0
T180	0	235	0	0
T181	0	17	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0
T219	0	8	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3621	0	0
T140	0	34	0	0
T149	0	47	0	0
T155	0	124	0	0
T157	0	12	0	0
T176	70455	36	0	0
T177	0	39	0	0
T178	0	11	0	0
T179	0	10	0	0
T180	0	248	0	0
T181	0	11	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3648	0	0
T140	0	31	0	0
T149	0	31	0	0
T155	0	132	0	0
T157	0	50	0	0
T176	70455	40	0	0
T177	0	25	0	0
T178	0	17	0	0
T179	0	2	0	0
T180	0	271	0	0
T181	0	13	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3611	0	0
T140	0	52	0	0
T149	0	47	0	0
T155	0	131	0	0
T157	0	37	0	0
T176	70455	64	0	0
T177	0	31	0	0
T178	0	17	0	0
T179	0	11	0	0
T180	0	207	0	0
T181	0	9	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3485	0	0
T140	0	25	0	0
T149	0	39	0	0
T155	0	139	0	0
T157	0	46	0	0
T176	70455	56	0	0
T177	0	26	0	0
T178	0	9	0	0
T179	0	1	0	0
T180	0	223	0	0
T181	0	9	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3517	0	0
T140	0	41	0	0
T149	0	39	0	0
T155	0	86	0	0
T157	0	33	0	0
T176	70455	55	0	0
T177	0	13	0	0
T178	0	10	0	0
T180	0	246	0	0
T181	0	10	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0
T201	0	10	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23487217	3578	0	0
T140	0	6	0	0
T149	0	32	0	0
T155	0	95	0	0
T157	0	44	0	0
T176	70455	52	0	0
T177	0	38	0	0
T178	0	15	0	0
T179	0	8	0	0
T180	0	221	0	0
T181	0	23	0	0
T182	12396	0	0	0
T183	5691	0	0	0
T184	3030	0	0	0
T185	3252	0	0	0
T186	16659	0	0	0
T187	119255	0	0	0
T188	3244	0	0	0
T189	59403	0	0	0
T190	2775	0	0	0