Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3445760	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

605937

1

T1

589

T2

521

T3

328

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3654200	1			T1	659		T2	557		T3	775
values[0x0]	197996	1			T1	253		T2	219		T3	60
values[0x1]	199501	1			T1	222		T2	220		T3	78

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2356441	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1695256

1

T1

742

T2

607

T3

448

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	64025	1			T2	1		T3	3		T5	6
valid_sources[0x01]	11588	1			T2	2		T3	2		T15	7
valid_sources[0x02]	14318	1			T2	6		T3	1		T5	5
valid_sources[0x03]	19249	1			T2	2		T3	3		T5	3
valid_sources[0x04]	10858	1			T2	2		T3	3		T5	7
valid_sources[0x05]	12804	1			T2	7		T5	8		T15	11
valid_sources[0x06]	12938	1			T2	4		T3	5		T5	4
valid_sources[0x07]	32752	1			T2	12		T3	2		T5	5
valid_sources[0x08]	13437	1			T2	3		T3	8		T5	7
valid_sources[0x09]	10960	1			T3	3		T5	3		T4	3
valid_sources[0x0a]	10090	1			T2	4		T3	2		T5	2
valid_sources[0x0b]	10628	1			T2	1		T3	4		T5	3
valid_sources[0x0c]	9956	1			T2	12		T3	6		T5	4
valid_sources[0x0d]	9624	1			T3	9		T5	5		T15	2
valid_sources[0x0e]	15615	1			T2	4		T3	6		T5	4
valid_sources[0x0f]	11517	1			T1	1134		T2	10		T3	6
valid_sources[0x10]	10132	1			T2	5		T3	3		T5	4
valid_sources[0x11]	11227	1			T2	1		T3	5		T5	3
valid_sources[0x12]	15411	1			T2	6		T3	1		T5	4
valid_sources[0x13]	11775	1			T3	4		T5	4		T4	3
valid_sources[0x14]	10632	1			T2	8		T5	6		T4	1
valid_sources[0x15]	21360	1			T2	3		T3	3		T5	2
valid_sources[0x16]	30480	1			T2	5		T3	2		T5	3
valid_sources[0x17]	12158	1			T2	14		T3	7		T5	3
valid_sources[0x18]	12331	1			T2	4		T3	4		T5	9
valid_sources[0x19]	12288	1			T2	6		T3	3		T5	4
valid_sources[0x1a]	10981	1			T2	6		T3	8		T5	5
valid_sources[0x1b]	12702	1			T2	1		T3	2		T5	4
valid_sources[0x1c]	10775	1			T3	6		T5	5		T4	8
valid_sources[0x1d]	10125	1			T2	1		T3	9		T5	4
valid_sources[0x1e]	10169	1			T2	4		T3	4		T5	9
valid_sources[0x1f]	11132	1			T2	2		T3	10		T5	5
valid_sources[0x20]	9136	1			T2	3		T5	4		T4	17
valid_sources[0x21]	10742	1			T2	1		T3	3		T5	6
valid_sources[0x22]	28540	1			T2	7		T3	2		T5	5
valid_sources[0x23]	11516	1			T3	2		T5	1		T15	1
valid_sources[0x24]	12594	1			T2	4		T3	3		T5	4
valid_sources[0x25]	12881	1			T2	1		T3	5		T5	7
valid_sources[0x26]	9734	1			T2	1		T3	5		T5	4
valid_sources[0x27]	9900	1			T3	2		T5	3		T4	33
valid_sources[0x28]	10993	1			T2	6		T3	1		T5	3
valid_sources[0x29]	11512	1			T2	1		T3	4		T5	3
valid_sources[0x2a]	9838	1			T3	5		T5	3		T4	16
valid_sources[0x2b]	12505	1			T2	1		T3	1		T5	6
valid_sources[0x2c]	10517	1			T2	9		T3	1		T5	3
valid_sources[0x2d]	9581	1			T2	8		T3	4		T5	7
valid_sources[0x2e]	14646	1			T2	8		T5	2		T4	6
valid_sources[0x2f]	12224	1			T3	1		T5	6		T4	20
valid_sources[0x30]	10047	1			T2	12		T3	3		T5	1
valid_sources[0x31]	10569	1			T2	7		T3	5		T5	6
valid_sources[0x32]	11319	1			T2	5		T3	4		T5	6
valid_sources[0x33]	10305	1			T2	1		T3	1		T5	5
valid_sources[0x34]	11638	1			T2	1		T3	2		T5	1
valid_sources[0x35]	9894	1			T2	5		T3	1		T5	1
valid_sources[0x36]	9832	1			T2	13		T3	4		T5	7
valid_sources[0x37]	9825	1			T3	3		T5	5		T4	4
valid_sources[0x38]	10811	1			T2	4		T3	3		T5	4
valid_sources[0x39]	10390	1			T2	1		T3	4		T5	3
valid_sources[0x3a]	12336	1			T2	1		T3	7		T5	6
valid_sources[0x3b]	11269	1			T2	1		T3	1		T5	4
valid_sources[0x3c]	16000	1			T3	6		T5	6		T15	5
valid_sources[0x3d]	12990	1			T5	5		T15	4		T18	4
valid_sources[0x3e]	11546	1			T2	8		T3	7		T5	1
valid_sources[0x3f]	20134	1			T3	5		T5	5		T4	30
valid_sources[0x40]	10679	1			T2	2		T3	3		T5	6
valid_sources[0x41]	10387	1			T3	1		T5	4		T15	2
valid_sources[0x42]	11386	1			T2	2		T3	8		T5	6
valid_sources[0x43]	11724	1			T2	1		T3	2		T5	5
valid_sources[0x44]	13850	1			T2	2		T3	7		T5	6
valid_sources[0x45]	77759	1			T2	7		T3	1		T5	1
valid_sources[0x46]	10197	1			T5	3		T15	4		T16	4
valid_sources[0x47]	10239	1			T2	9		T3	4		T5	4
valid_sources[0x48]	71036	1			T3	4		T5	5		T4	9
valid_sources[0x49]	10363	1			T2	2		T3	3		T5	2
valid_sources[0x4a]	12293	1			T3	4		T5	1		T15	2
valid_sources[0x4b]	10827	1			T2	3		T3	2		T5	3
valid_sources[0x4c]	11671	1			T2	2		T3	3		T5	5
valid_sources[0x4d]	11759	1			T2	1		T3	2		T5	4
valid_sources[0x4e]	11503	1			T2	9		T3	8		T5	6
valid_sources[0x4f]	14322	1			T2	6		T3	2		T5	3
valid_sources[0x50]	15279	1			T2	1		T3	7		T5	6
valid_sources[0x51]	14452	1			T2	3		T5	4		T4	25
valid_sources[0x52]	112338	1			T2	1		T3	2		T5	4
valid_sources[0x53]	10441	1			T2	2		T3	4		T5	4
valid_sources[0x54]	10535	1			T2	7		T3	2		T5	3
valid_sources[0x55]	20433	1			T2	6		T3	3		T5	4
valid_sources[0x56]	13534	1			T2	9		T3	1		T5	5
valid_sources[0x57]	15834	1			T2	4		T3	4		T5	1
valid_sources[0x58]	11088	1			T3	11		T5	4		T4	2
valid_sources[0x59]	25927	1			T2	8		T5	6		T4	23
valid_sources[0x5a]	10896	1			T2	7		T3	3		T5	5
valid_sources[0x5b]	10462	1			T3	4		T5	7		T17	31
valid_sources[0x5c]	10915	1			T2	3		T5	7		T4	17
valid_sources[0x5d]	10698	1			T2	3		T3	3		T5	1
valid_sources[0x5e]	9642	1			T3	1		T5	3		T15	6
valid_sources[0x5f]	10925	1			T2	1		T3	1		T5	2
valid_sources[0x60]	14805	1			T2	3		T3	2		T5	2
valid_sources[0x61]	9613	1			T3	3		T5	3		T4	43
valid_sources[0x62]	17819	1			T2	2		T5	4		T4	10
valid_sources[0x63]	10097	1			T3	4		T5	5		T15	8
valid_sources[0x64]	10676	1			T3	4		T5	1		T4	24
valid_sources[0x65]	10210	1			T2	6		T3	1		T5	6
valid_sources[0x66]	10585	1			T2	3		T3	6		T5	2
valid_sources[0x67]	10005	1			T2	3		T3	5		T5	2
valid_sources[0x68]	12347	1			T2	4		T3	11		T5	4
valid_sources[0x69]	16584	1			T2	2		T3	6		T5	3
valid_sources[0x6a]	10215	1			T2	2		T3	4		T5	5
valid_sources[0x6b]	16044	1			T2	7		T5	6		T4	2
valid_sources[0x6c]	13363	1			T2	2		T3	3		T5	5
valid_sources[0x6d]	16070	1			T3	3		T5	7		T15	6
valid_sources[0x6e]	13014	1			T2	4		T3	4		T5	6
valid_sources[0x6f]	14066	1			T2	4		T3	3		T5	1
valid_sources[0x70]	11148	1			T2	1		T3	5		T5	4
valid_sources[0x71]	9459	1			T2	2		T3	10		T5	6
valid_sources[0x72]	14251	1			T2	2		T3	6		T5	2
valid_sources[0x73]	10572	1			T2	3		T3	1		T5	1
valid_sources[0x74]	13809	1			T2	8		T3	4		T5	3
valid_sources[0x75]	11560	1			T2	1		T3	5		T5	4
valid_sources[0x76]	11615	1			T2	3		T3	15		T5	10
valid_sources[0x77]	14707	1			T3	3		T5	1		T15	8
valid_sources[0x78]	14041	1			T2	1		T3	6		T5	3
valid_sources[0x79]	10267	1			T2	2		T3	4		T5	5
valid_sources[0x7a]	10923	1			T2	1		T3	5		T5	6
valid_sources[0x7b]	11101	1			T2	5		T3	4		T5	3
valid_sources[0x7c]	16917	1			T2	8		T3	3		T5	7
valid_sources[0x7d]	10697	1			T3	2		T5	4		T4	23
valid_sources[0x7e]	10750	1			T2	1		T3	2		T5	4
valid_sources[0x7f]	10315	1			T3	1		T5	2		T15	5
valid_sources[0x80]	15111	1			T2	8		T3	1		T5	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

336520

1

T1

221

T2

253

T3

292

values[0x0]

all_enables

biggest_size

142126

1

T1

198

T2

142

T3

17

values[0x1]

all_enables

biggest_size

127291

1

T1

170

T2

126

T3

19