Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
22393006 |
22227738 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
22227738 |
0 |
0 |
T1 |
4097 |
4031 |
0 |
0 |
T2 |
9706 |
9552 |
0 |
0 |
T3 |
8105 |
8047 |
0 |
0 |
T4 |
11178 |
11102 |
0 |
0 |
T5 |
3534 |
3367 |
0 |
0 |
T15 |
12174 |
11999 |
0 |
0 |
T16 |
5204 |
5145 |
0 |
0 |
T17 |
18727 |
18565 |
0 |
0 |
T18 |
8980 |
8910 |
0 |
0 |
T19 |
2958 |
2875 |
0 |
0 |