Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3750713	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

617527

1

T1

166

T2

653

T3

350

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3953785	1			T1	543		T2	683		T3	729
values[0x0]	206269	1			T1	39		T2	244		T3	82
values[0x1]	208186	1			T1	45		T2	261		T3	79

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2559538	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1808702

1

T1

290

T2

757

T3

494

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14694	1			T2	2		T3	4		T15	25
valid_sources[0x01]	16489	1			T2	1		T3	2		T15	31
valid_sources[0x02]	14353	1			T1	8		T2	9		T3	4
valid_sources[0x03]	27243	1			T1	8		T2	7		T3	2
valid_sources[0x04]	55549	1			T2	6		T3	5		T4	43
valid_sources[0x05]	14230	1			T3	1		T4	13		T15	17
valid_sources[0x06]	14899	1			T2	3		T3	1		T15	56
valid_sources[0x07]	13524	1			T2	2		T3	3		T15	25
valid_sources[0x08]	14816	1			T2	1		T3	6		T15	18
valid_sources[0x09]	14507	1			T2	2		T3	6		T15	38
valid_sources[0x0a]	13951	1			T2	4		T3	3		T15	30
valid_sources[0x0b]	13086	1			T2	1		T3	6		T15	12
valid_sources[0x0c]	13596	1			T1	4		T2	8		T3	2
valid_sources[0x0d]	13979	1			T2	3		T3	3		T4	61
valid_sources[0x0e]	15309	1			T3	5		T15	27		T5	4
valid_sources[0x0f]	14263	1			T2	3		T3	3		T15	38
valid_sources[0x10]	17522	1			T1	1		T2	2		T3	5
valid_sources[0x11]	13396	1			T2	7		T3	1		T15	45
valid_sources[0x12]	15293	1			T1	2		T3	1		T15	23
valid_sources[0x13]	13330	1			T2	5		T3	2		T15	29
valid_sources[0x14]	17797	1			T1	4		T3	3		T15	33
valid_sources[0x15]	14765	1			T1	3		T2	3		T3	4
valid_sources[0x16]	13278	1			T2	5		T3	5		T15	49
valid_sources[0x17]	14062	1			T1	1		T2	3		T3	7
valid_sources[0x18]	14860	1			T1	2		T2	7		T3	5
valid_sources[0x19]	13513	1			T2	3		T3	7		T4	16
valid_sources[0x1a]	14540	1			T1	2		T2	1		T3	2
valid_sources[0x1b]	13919	1			T1	4		T2	7		T3	3
valid_sources[0x1c]	14045	1			T1	7		T2	2		T3	3
valid_sources[0x1d]	14021	1			T2	1		T3	4		T15	21
valid_sources[0x1e]	16885	1			T1	1		T2	10		T3	3
valid_sources[0x1f]	15375	1			T1	1		T2	3		T3	4
valid_sources[0x20]	14927	1			T2	2		T3	2		T15	34
valid_sources[0x21]	13957	1			T1	7		T2	7		T3	5
valid_sources[0x22]	21791	1			T1	1		T2	2		T3	2
valid_sources[0x23]	14308	1			T2	2		T3	4		T15	41
valid_sources[0x24]	12922	1			T2	4		T3	1		T15	27
valid_sources[0x25]	17415	1			T1	10		T3	5		T15	25
valid_sources[0x26]	14066	1			T1	3		T2	2		T3	7
valid_sources[0x27]	32655	1			T1	2		T3	2		T15	29
valid_sources[0x28]	14881	1			T2	5		T3	3		T4	40
valid_sources[0x29]	13972	1			T1	5		T2	9		T3	8
valid_sources[0x2a]	18141	1			T1	5		T2	6		T3	5
valid_sources[0x2b]	14552	1			T1	3		T2	7		T3	4
valid_sources[0x2c]	13162	1			T1	1		T2	6		T3	1
valid_sources[0x2d]	14140	1			T1	9		T2	5		T3	2
valid_sources[0x2e]	13782	1			T1	4		T2	5		T3	4
valid_sources[0x2f]	18723	1			T3	5		T15	50		T5	1
valid_sources[0x30]	15396	1			T2	7		T3	5		T15	27
valid_sources[0x31]	16391	1			T2	1		T3	2		T15	38
valid_sources[0x32]	14252	1			T1	5		T2	1		T15	35
valid_sources[0x33]	13986	1			T1	3		T2	4		T3	1
valid_sources[0x34]	20588	1			T1	8		T2	3		T15	36
valid_sources[0x35]	13529	1			T1	4		T2	1		T3	4
valid_sources[0x36]	16941	1			T1	1		T2	3		T3	3
valid_sources[0x37]	15352	1			T1	7		T2	4		T3	5
valid_sources[0x38]	14949	1			T1	4		T2	8		T3	2
valid_sources[0x39]	14323	1			T1	1		T2	4		T3	4
valid_sources[0x3a]	30482	1			T1	11		T2	15		T3	5
valid_sources[0x3b]	14932	1			T1	3		T2	10		T3	2
valid_sources[0x3c]	14254	1			T2	8		T3	3		T15	57
valid_sources[0x3d]	14344	1			T1	3		T2	3		T3	5
valid_sources[0x3e]	13248	1			T1	8		T2	7		T3	5
valid_sources[0x3f]	13635	1			T1	14		T2	10		T3	4
valid_sources[0x40]	13600	1			T1	5		T3	6		T15	24
valid_sources[0x41]	140176	1			T2	1		T3	2		T15	36
valid_sources[0x42]	86088	1			T2	4		T3	4		T15	24
valid_sources[0x43]	14330	1			T1	1		T2	9		T3	3
valid_sources[0x44]	14037	1			T2	5		T3	3		T15	32
valid_sources[0x45]	13381	1			T1	2		T2	2		T3	2
valid_sources[0x46]	15209	1			T1	7		T2	5		T3	2
valid_sources[0x47]	14120	1			T2	2		T3	3		T15	28
valid_sources[0x48]	13792	1			T2	5		T3	4		T15	15
valid_sources[0x49]	14334	1			T2	12		T3	2		T15	52
valid_sources[0x4a]	13928	1			T2	12		T3	3		T15	5
valid_sources[0x4b]	13735	1			T1	3		T2	4		T3	2
valid_sources[0x4c]	17354	1			T1	3		T2	3		T3	2
valid_sources[0x4d]	15041	1			T1	1		T2	4		T3	3
valid_sources[0x4e]	17433	1			T1	5		T2	5		T3	6
valid_sources[0x4f]	19329	1			T1	2		T2	5		T3	6
valid_sources[0x50]	14338	1			T2	4		T3	2		T15	37
valid_sources[0x51]	21635	1			T2	4		T3	1		T15	40
valid_sources[0x52]	13552	1			T1	12		T2	4		T3	6
valid_sources[0x53]	16495	1			T2	1		T3	5		T4	2
valid_sources[0x54]	13855	1			T1	4		T2	9		T3	2
valid_sources[0x55]	32964	1			T1	2		T2	7		T3	6
valid_sources[0x56]	15116	1			T1	1		T2	5		T3	2
valid_sources[0x57]	13841	1			T1	3		T2	8		T3	4
valid_sources[0x58]	13875	1			T2	3		T3	1		T15	21
valid_sources[0x59]	14206	1			T1	5		T2	5		T3	5
valid_sources[0x5a]	14868	1			T1	1		T2	5		T3	4
valid_sources[0x5b]	15676	1			T1	2		T2	8		T3	3
valid_sources[0x5c]	16169	1			T1	1		T2	8		T3	4
valid_sources[0x5d]	15010	1			T2	2		T3	3		T15	34
valid_sources[0x5e]	14058	1			T1	1		T2	3		T3	4
valid_sources[0x5f]	14102	1			T1	6		T2	3		T3	4
valid_sources[0x60]	15095	1			T2	4		T3	3		T15	20
valid_sources[0x61]	25537	1			T1	12		T2	2		T3	3
valid_sources[0x62]	13360	1			T1	2		T2	7		T3	7
valid_sources[0x63]	14040	1			T2	8		T3	5		T15	18
valid_sources[0x64]	13718	1			T2	4		T3	3		T4	14
valid_sources[0x65]	13102	1			T1	2		T2	2		T3	5
valid_sources[0x66]	16579	1			T1	9		T2	5		T3	3
valid_sources[0x67]	13478	1			T2	3		T3	3		T15	41
valid_sources[0x68]	13353	1			T1	5		T2	6		T3	6
valid_sources[0x69]	15480	1			T2	7		T3	7		T15	57
valid_sources[0x6a]	32176	1			T1	7		T2	3		T15	30
valid_sources[0x6b]	14101	1			T1	1		T2	2		T3	3
valid_sources[0x6c]	23548	1			T1	4		T2	5		T3	4
valid_sources[0x6d]	46089	1			T2	5		T3	2		T15	27
valid_sources[0x6e]	13857	1			T1	8		T2	3		T3	5
valid_sources[0x6f]	15236	1			T2	9		T3	4		T4	30
valid_sources[0x70]	13386	1			T1	5		T3	6		T4	3
valid_sources[0x71]	16072	1			T2	4		T3	3		T15	49
valid_sources[0x72]	13392	1			T1	3		T2	4		T3	2
valid_sources[0x73]	24638	1			T1	6		T2	6		T3	4
valid_sources[0x74]	13794	1			T1	1		T2	2		T3	1
valid_sources[0x75]	16721	1			T1	2		T2	5		T3	3
valid_sources[0x76]	13648	1			T1	1		T2	8		T3	1
valid_sources[0x77]	14132	1			T1	3		T2	3		T3	2
valid_sources[0x78]	14068	1			T2	6		T3	6		T4	40
valid_sources[0x79]	14457	1			T2	4		T3	3		T15	20
valid_sources[0x7a]	13667	1			T1	1		T2	7		T3	4
valid_sources[0x7b]	49125	1			T1	2		T2	7		T3	4
valid_sources[0x7c]	13532	1			T3	4		T15	10		T16	31
valid_sources[0x7d]	13742	1			T2	3		T3	3		T15	35
valid_sources[0x7e]	14775	1			T1	1		T2	1		T3	1
valid_sources[0x7f]	13325	1			T2	6		T3	6		T15	38
valid_sources[0x80]	13334	1			T2	5		T3	3		T15	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

335629

1

T1

147

T2

327

T3

291

values[0x0]

all_enables

biggest_size

148344

1

T1

12

T2

168

T3

34

values[0x1]

all_enables

biggest_size

133554

1

T1

7

T2

158

T3

25