Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
28809978 |
28654900 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
28809978 |
28654900 |
0 |
0 |
T1 |
5706 |
5616 |
0 |
0 |
T2 |
9325 |
9193 |
0 |
0 |
T3 |
4634 |
4485 |
0 |
0 |
T4 |
5877 |
5791 |
0 |
0 |
T5 |
8798 |
8745 |
0 |
0 |
T15 |
65876 |
65783 |
0 |
0 |
T16 |
21296 |
21133 |
0 |
0 |
T17 |
47670 |
47602 |
0 |
0 |
T18 |
2519 |
2423 |
0 |
0 |
T19 |
9571 |
9498 |
0 |
0 |