Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3272037	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

649035

1

T1

262

T2

754

T3

263

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3491896	1			T1	1659		T2	1027		T3	231
values[0x0]	212767	1			T1	66		T2	247		T3	126
values[0x1]	216409	1			T1	67		T2	214		T3	129

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2243133	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1677939

1

T1

722

T2

886

T3

317

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	40554	1			T1	7		T4	12		T12	13
valid_sources[0x01]	13894	1			T1	11		T4	14		T12	13
valid_sources[0x02]	13387	1			T1	2		T2	12		T4	10
valid_sources[0x03]	14296	1			T1	5		T4	15		T12	13
valid_sources[0x04]	14438	1			T1	9		T4	9		T12	8
valid_sources[0x05]	12513	1			T1	6		T4	8		T12	15
valid_sources[0x06]	13006	1			T1	5		T4	15		T12	10
valid_sources[0x07]	19084	1			T1	8		T4	10		T12	9
valid_sources[0x08]	13164	1			T1	7		T4	1		T12	10
valid_sources[0x09]	13717	1			T1	6		T4	8		T12	12
valid_sources[0x0a]	12838	1			T1	5		T4	4		T12	12
valid_sources[0x0b]	12533	1			T1	10		T4	4		T12	11
valid_sources[0x0c]	24686	1			T1	8		T2	1		T4	3
valid_sources[0x0d]	13180	1			T1	18		T4	8		T12	12
valid_sources[0x0e]	13985	1			T1	3		T4	17		T12	10
valid_sources[0x0f]	14517	1			T1	6		T4	8		T12	6
valid_sources[0x10]	12330	1			T1	4		T4	11		T12	12
valid_sources[0x11]	12739	1			T1	7		T4	8		T12	15
valid_sources[0x12]	13862	1			T1	5		T4	11		T12	10
valid_sources[0x13]	12519	1			T1	4		T4	16		T12	10
valid_sources[0x14]	13046	1			T1	6		T2	1		T4	5
valid_sources[0x15]	12421	1			T1	5		T4	4		T12	11
valid_sources[0x16]	12955	1			T1	9		T4	8		T12	11
valid_sources[0x17]	13293	1			T1	13		T4	14		T12	10
valid_sources[0x18]	13121	1			T1	6		T4	8		T12	12
valid_sources[0x19]	14152	1			T1	5		T2	2		T4	1
valid_sources[0x1a]	17581	1			T1	8		T4	11		T12	9
valid_sources[0x1b]	13521	1			T1	12		T2	28		T4	6
valid_sources[0x1c]	13267	1			T1	7		T4	16		T12	13
valid_sources[0x1d]	14163	1			T1	3		T4	16		T12	12
valid_sources[0x1e]	14404	1			T1	4		T4	10		T12	12
valid_sources[0x1f]	13695	1			T1	8		T3	486		T4	6
valid_sources[0x20]	12983	1			T1	11		T4	9		T12	9
valid_sources[0x21]	19348	1			T1	9		T4	9		T12	9
valid_sources[0x22]	13793	1			T1	7		T4	10		T12	10
valid_sources[0x23]	31699	1			T1	8		T4	9		T12	8
valid_sources[0x24]	17649	1			T1	4		T4	13		T12	7
valid_sources[0x25]	14127	1			T1	4		T4	2		T12	10
valid_sources[0x26]	12876	1			T1	7		T4	11		T12	18
valid_sources[0x27]	18525	1			T1	15		T4	11		T12	10
valid_sources[0x28]	12498	1			T1	7		T4	6		T12	13
valid_sources[0x29]	13167	1			T1	4		T4	6		T12	6
valid_sources[0x2a]	12736	1			T1	7		T2	5		T4	18
valid_sources[0x2b]	13800	1			T1	11		T4	11		T12	13
valid_sources[0x2c]	13085	1			T1	9		T4	5		T12	11
valid_sources[0x2d]	13021	1			T1	8		T4	11		T12	17
valid_sources[0x2e]	13564	1			T1	7		T2	9		T4	19
valid_sources[0x2f]	13503	1			T1	9		T4	15		T12	13
valid_sources[0x30]	12797	1			T1	3		T4	8		T12	15
valid_sources[0x31]	14072	1			T1	8		T4	6		T12	14
valid_sources[0x32]	13620	1			T1	9		T4	8		T12	17
valid_sources[0x33]	12585	1			T1	5		T4	3		T12	10
valid_sources[0x34]	16112	1			T1	11		T4	7		T12	14
valid_sources[0x35]	14120	1			T1	7		T4	8		T12	12
valid_sources[0x36]	12914	1			T1	15		T4	14		T12	15
valid_sources[0x37]	12892	1			T1	9		T2	1		T4	6
valid_sources[0x38]	18311	1			T1	4		T4	19		T12	8
valid_sources[0x39]	12853	1			T1	8		T4	14		T12	15
valid_sources[0x3a]	13588	1			T1	7		T4	10		T12	16
valid_sources[0x3b]	14504	1			T1	7		T4	7		T12	10
valid_sources[0x3c]	17900	1			T1	3		T4	4		T12	11
valid_sources[0x3d]	13734	1			T1	9		T4	10		T12	12
valid_sources[0x3e]	13062	1			T1	5		T4	8		T12	9
valid_sources[0x3f]	13745	1			T1	2		T4	14		T12	15
valid_sources[0x40]	13636	1			T1	3		T4	9		T12	9
valid_sources[0x41]	13192	1			T1	3		T4	10		T12	7
valid_sources[0x42]	12929	1			T1	7		T4	15		T12	20
valid_sources[0x43]	13065	1			T1	6		T4	8		T12	13
valid_sources[0x44]	14701	1			T1	5		T4	8		T12	15
valid_sources[0x45]	13670	1			T1	4		T4	10		T12	20
valid_sources[0x46]	18435	1			T1	3		T4	12		T12	14
valid_sources[0x47]	13625	1			T1	8		T2	3		T4	5
valid_sources[0x48]	12756	1			T1	6		T2	5		T4	8
valid_sources[0x49]	13227	1			T1	3		T2	8		T4	19
valid_sources[0x4a]	14958	1			T1	9		T4	6		T12	11
valid_sources[0x4b]	16043	1			T1	7		T4	7		T12	7
valid_sources[0x4c]	26308	1			T1	8		T4	10		T12	8
valid_sources[0x4d]	12974	1			T1	9		T4	8		T12	8
valid_sources[0x4e]	12330	1			T1	8		T4	4		T12	9
valid_sources[0x4f]	14217	1			T1	6		T4	9		T12	14
valid_sources[0x50]	18344	1			T1	8		T4	15		T12	7
valid_sources[0x51]	37283	1			T1	3		T4	10		T12	12
valid_sources[0x52]	13788	1			T1	7		T4	11		T12	12
valid_sources[0x53]	15384	1			T1	9		T4	11		T12	12
valid_sources[0x54]	13322	1			T1	6		T4	19		T12	13
valid_sources[0x55]	12815	1			T1	6		T4	11		T12	11
valid_sources[0x56]	12601	1			T1	8		T4	12		T12	15
valid_sources[0x57]	12975	1			T1	6		T4	4		T12	13
valid_sources[0x58]	14347	1			T1	3		T4	11		T12	17
valid_sources[0x59]	16004	1			T1	12		T2	5		T4	12
valid_sources[0x5a]	17585	1			T1	8		T4	11		T12	7
valid_sources[0x5b]	13174	1			T1	6		T4	8		T12	12
valid_sources[0x5c]	12993	1			T1	5		T4	16		T12	6
valid_sources[0x5d]	19322	1			T1	6		T4	8		T12	14
valid_sources[0x5e]	18274	1			T1	3		T4	4		T12	8
valid_sources[0x5f]	48079	1			T1	7		T4	9		T12	8
valid_sources[0x60]	15554	1			T1	7		T4	18		T12	10
valid_sources[0x61]	14092	1			T1	7		T4	16		T12	15
valid_sources[0x62]	24855	1			T1	12		T4	7		T12	11
valid_sources[0x63]	38158	1			T1	3		T2	12		T4	6
valid_sources[0x64]	14461	1			T1	5		T4	9		T12	13
valid_sources[0x65]	12819	1			T1	8		T2	1		T4	22
valid_sources[0x66]	14311	1			T1	3		T4	19		T12	7
valid_sources[0x67]	12953	1			T1	9		T4	11		T12	13
valid_sources[0x68]	23265	1			T1	10		T4	6		T12	15
valid_sources[0x69]	13599	1			T1	4		T2	151		T4	13
valid_sources[0x6a]	12893	1			T1	10		T4	15		T12	14
valid_sources[0x6b]	16756	1			T1	7		T4	9		T12	12
valid_sources[0x6c]	12315	1			T1	3		T4	10		T12	10
valid_sources[0x6d]	13014	1			T1	8		T4	7		T12	10
valid_sources[0x6e]	13150	1			T1	11		T4	5		T12	8
valid_sources[0x6f]	15728	1			T1	5		T2	2		T4	14
valid_sources[0x70]	14250	1			T1	6		T4	13		T12	10
valid_sources[0x71]	12569	1			T1	1		T2	46		T4	6
valid_sources[0x72]	12782	1			T1	9		T4	16		T12	10
valid_sources[0x73]	18003	1			T1	6		T2	681		T4	15
valid_sources[0x74]	12138	1			T1	7		T4	7		T12	14
valid_sources[0x75]	15647	1			T1	5		T2	8		T4	14
valid_sources[0x76]	17393	1			T1	10		T4	6		T12	11
valid_sources[0x77]	15918	1			T1	7		T4	11		T12	9
valid_sources[0x78]	13771	1			T1	5		T4	10		T12	9
valid_sources[0x79]	12504	1			T1	7		T4	4		T12	13
valid_sources[0x7a]	13231	1			T1	10		T4	9		T12	9
valid_sources[0x7b]	17959	1			T1	6		T4	12		T12	10
valid_sources[0x7c]	17781	1			T1	5		T4	9		T12	12
valid_sources[0x7d]	13276	1			T1	13		T4	21		T12	15
valid_sources[0x7e]	13159	1			T1	10		T2	1		T4	13
valid_sources[0x7f]	14431	1			T1	7		T4	13		T12	13
valid_sources[0x80]	16026	1			T1	5		T2	387		T4	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

355647

1

T1

223

T2

433

T3

85

values[0x0]

all_enables

biggest_size

154189

1

T1

27

T2

178

T3

93

values[0x1]

all_enables

biggest_size

139199

1

T1

12

T2

143

T3

85