Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
24961696 |
24802648 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
24961696 |
24802648 |
0 |
0 |
T1 |
14688 |
14632 |
0 |
0 |
T2 |
14147 |
14071 |
0 |
0 |
T3 |
4712 |
4654 |
0 |
0 |
T4 |
22038 |
21970 |
0 |
0 |
T12 |
32503 |
32414 |
0 |
0 |
T13 |
21818 |
21710 |
0 |
0 |
T14 |
5391 |
5243 |
0 |
0 |
T15 |
4578 |
4521 |
0 |
0 |
T16 |
6844 |
6750 |
0 |
0 |
T17 |
5096 |
4919 |
0 |
0 |