Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26905409	18789	0	0
attest_sw_binding_0_rd_A	26905409	2779	0	0
attest_sw_binding_1_rd_A	26905409	2927	0	0
attest_sw_binding_2_rd_A	26905409	2903	0	0
attest_sw_binding_3_rd_A	26905409	2724	0	0
attest_sw_binding_4_rd_A	26905409	2908	0	0
attest_sw_binding_5_rd_A	26905409	2919	0	0
attest_sw_binding_6_rd_A	26905409	2663	0	0
attest_sw_binding_7_rd_A	26905409	2774	0	0
intr_enable_rd_A	26905409	3724	0	0
key_version_rd_A	26905409	2785	0	0
max_creator_key_ver_regwen_rd_A	26905409	2867	0	0
max_owner_int_key_ver_regwen_rd_A	26905409	2835	0	0
max_owner_key_ver_regwen_rd_A	26905409	2806	0	0
reseed_interval_regwen_rd_A	26905409	2908	0	0
salt_0_rd_A	26905409	2753	0	0
salt_1_rd_A	26905409	2955	0	0
salt_2_rd_A	26905409	2888	0	0
salt_3_rd_A	26905409	2866	0	0
salt_4_rd_A	26905409	2909	0	0
salt_5_rd_A	26905409	3017	0	0
salt_6_rd_A	26905409	2779	0	0
salt_7_rd_A	26905409	2899	0	0
sealing_sw_binding_0_rd_A	26905409	2814	0	0
sealing_sw_binding_1_rd_A	26905409	2821	0	0
sealing_sw_binding_2_rd_A	26905409	3021	0	0
sealing_sw_binding_3_rd_A	26905409	2719	0	0
sealing_sw_binding_4_rd_A	26905409	2824	0	0
sealing_sw_binding_5_rd_A	26905409	2706	0	0
sealing_sw_binding_6_rd_A	26905409	2906	0	0
sealing_sw_binding_7_rd_A	26905409	2825	0	0
sideload_clear_rd_A	26905409	2775	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	18789	0	0
T12	32503	25	0	0
T13	21818	21	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T54	0	25	0	0
T65	0	161	0	0
T84	15758	0	0	0
T104	0	27	0	0
T112	0	63	0	0
T122	0	177	0	0
T123	0	1235	0	0
T124	0	435	0	0
T125	0	119	0	0
T126	69820	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2779	0	0
T12	32503	29	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	4	0	0
T117	0	13	0	0
T126	69820	0	0	0
T184	0	26	0	0
T185	0	45	0	0
T186	0	32	0	0
T187	0	10	0	0
T188	0	12	0	0
T189	0	64	0	0
T190	0	13	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2927	0	0
T12	32503	50	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	26	0	0
T117	0	13	0	0
T126	69820	0	0	0
T184	0	37	0	0
T185	0	58	0	0
T186	0	55	0	0
T187	0	15	0	0
T188	0	16	0	0
T189	0	52	0	0
T190	0	16	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2903	0	0
T12	32503	12	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	10	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	15	0	0
T126	69820	0	0	0
T184	0	60	0	0
T185	0	27	0	0
T186	0	30	0	0
T187	0	29	0	0
T188	0	23	0	0
T189	0	59	0	0
T190	0	14	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2724	0	0
T12	32503	21	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	13	0	0
T117	0	18	0	0
T126	69820	0	0	0
T184	0	21	0	0
T185	0	19	0	0
T186	0	63	0	0
T187	0	23	0	0
T188	0	9	0	0
T189	0	66	0	0
T190	0	20	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2908	0	0
T12	32503	13	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	7	0	0
T126	69820	0	0	0
T184	0	29	0	0
T185	0	30	0	0
T186	0	65	0	0
T187	0	31	0	0
T188	0	12	0	0
T189	0	61	0	0
T190	0	20	0	0
T191	0	5	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2919	0	0
T12	32503	31	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	5	0	0
T126	69820	0	0	0
T184	0	38	0	0
T185	0	29	0	0
T186	0	69	0	0
T187	0	18	0	0
T188	0	26	0	0
T189	0	81	0	0
T190	0	16	0	0
T191	0	10	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2663	0	0
T12	32503	35	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	6	0	0
T126	69820	0	0	0
T184	0	23	0	0
T185	0	28	0	0
T186	0	44	0	0
T187	0	12	0	0
T188	0	12	0	0
T189	0	61	0	0
T190	0	23	0	0
T191	0	5	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2774	0	0
T12	32503	15	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	17	0	0
T126	69820	0	0	0
T184	0	23	0	0
T185	0	32	0	0
T186	0	84	0	0
T187	0	30	0	0
T188	0	6	0	0
T189	0	61	0	0
T190	0	9	0	0
T191	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	3724	0	0
T12	32503	19	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T59	0	22	0	0
T69	0	10	0	0
T84	15758	0	0	0
T104	0	47	0	0
T126	69820	0	0	0
T184	0	42	0	0
T192	0	56	0	0
T193	0	26	0	0
T194	0	44	0	0
T195	0	15	0	0
T196	0	27	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2785	0	0
T12	32503	21	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	10	0	0
T117	0	23	0	0
T126	69820	0	0	0
T184	0	18	0	0
T185	0	41	0	0
T186	0	59	0	0
T187	0	16	0	0
T188	0	10	0	0
T189	0	50	0	0
T190	0	11	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2867	0	0
T12	32503	19	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	16	0	0
T117	0	20	0	0
T126	69820	0	0	0
T184	0	25	0	0
T185	0	23	0	0
T186	0	52	0	0
T187	0	5	0	0
T188	0	21	0	0
T189	0	80	0	0
T190	0	10	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2835	0	0
T12	32503	45	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	12	0	0
T117	0	15	0	0
T126	69820	0	0	0
T184	0	41	0	0
T185	0	34	0	0
T186	0	41	0	0
T187	0	6	0	0
T188	0	4	0	0
T189	0	66	0	0
T190	0	20	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2806	0	0
T12	32503	9	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	10	0	0
T126	69820	0	0	0
T184	0	16	0	0
T185	0	55	0	0
T186	0	45	0	0
T187	0	2	0	0
T188	0	16	0	0
T189	0	61	0	0
T190	0	22	0	0
T191	0	5	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2908	0	0
T12	32503	26	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	21	0	0
T126	69820	0	0	0
T184	0	49	0	0
T185	0	20	0	0
T186	0	81	0	0
T187	0	25	0	0
T188	0	17	0	0
T189	0	70	0	0
T190	0	19	0	0
T191	0	16	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2753	0	0
T12	32503	25	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	13	0	0
T126	69820	0	0	0
T184	0	34	0	0
T185	0	41	0	0
T186	0	44	0	0
T187	0	26	0	0
T188	0	1	0	0
T189	0	82	0	0
T191	0	5	0	0
T197	0	6	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2955	0	0
T12	32503	46	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	15	0	0
T126	69820	0	0	0
T184	0	50	0	0
T185	0	39	0	0
T186	0	84	0	0
T187	0	16	0	0
T188	0	13	0	0
T189	0	44	0	0
T190	0	13	0	0
T191	0	19	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2888	0	0
T12	32503	23	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	15	0	0
T126	69820	0	0	0
T184	0	32	0	0
T185	0	21	0	0
T186	0	89	0	0
T187	0	20	0	0
T188	0	8	0	0
T189	0	45	0	0
T190	0	18	0	0
T191	0	1	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2866	0	0
T12	32503	36	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	1	0	0
T126	69820	0	0	0
T184	0	36	0	0
T185	0	4	0	0
T186	0	88	0	0
T187	0	7	0	0
T188	0	15	0	0
T189	0	68	0	0
T191	0	1	0	0
T198	0	1	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2909	0	0
T12	32503	22	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	13	0	0
T126	69820	0	0	0
T184	0	61	0	0
T185	0	42	0	0
T186	0	69	0	0
T187	0	26	0	0
T188	0	12	0	0
T189	0	43	0	0
T190	0	17	0	0
T191	0	6	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	3017	0	0
T12	32503	24	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	14	0	0
T126	69820	0	0	0
T184	0	5	0	0
T185	0	55	0	0
T186	0	67	0	0
T187	0	5	0	0
T188	0	13	0	0
T189	0	92	0	0
T190	0	18	0	0
T191	0	7	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2779	0	0
T12	32503	32	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	19	0	0
T117	0	22	0	0
T126	69820	0	0	0
T184	0	32	0	0
T185	0	18	0	0
T186	0	55	0	0
T187	0	5	0	0
T188	0	16	0	0
T189	0	60	0	0
T190	0	11	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2899	0	0
T12	32503	22	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	17	0	0
T126	69820	0	0	0
T184	0	23	0	0
T185	0	38	0	0
T186	0	80	0	0
T187	0	17	0	0
T188	0	19	0	0
T189	0	26	0	0
T190	0	15	0	0
T191	0	9	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2814	0	0
T12	32503	46	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	20	0	0
T126	69820	0	0	0
T184	0	29	0	0
T185	0	49	0	0
T186	0	68	0	0
T187	0	14	0	0
T188	0	12	0	0
T189	0	54	0	0
T190	0	14	0	0
T191	0	4	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2821	0	0
T12	32503	22	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	35	0	0
T126	69820	0	0	0
T184	0	18	0	0
T185	0	15	0	0
T186	0	52	0	0
T187	0	2	0	0
T188	0	5	0	0
T189	0	41	0	0
T190	0	23	0	0
T191	0	8	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	3021	0	0
T12	32503	23	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	17	0	0
T126	69820	0	0	0
T184	0	22	0	0
T185	0	13	0	0
T186	0	57	0	0
T187	0	6	0	0
T188	0	21	0	0
T189	0	67	0	0
T190	0	23	0	0
T191	0	5	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2719	0	0
T12	32503	22	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	12	0	0
T126	69820	0	0	0
T184	0	26	0	0
T185	0	37	0	0
T186	0	53	0	0
T187	0	8	0	0
T188	0	12	0	0
T189	0	85	0	0
T190	0	18	0	0
T199	0	5	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2824	0	0
T12	32503	22	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	13	0	0
T126	69820	0	0	0
T184	0	39	0	0
T185	0	31	0	0
T186	0	62	0	0
T187	0	43	0	0
T188	0	16	0	0
T189	0	43	0	0
T190	0	13	0	0
T191	0	3	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2706	0	0
T12	32503	21	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	17	0	0
T126	69820	0	0	0
T184	0	19	0	0
T185	0	35	0	0
T186	0	62	0	0
T187	0	7	0	0
T188	0	2	0	0
T189	0	42	0	0
T190	0	14	0	0
T191	0	10	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2906	0	0
T12	32503	25	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	36	0	0
T117	0	16	0	0
T126	69820	0	0	0
T184	0	37	0	0
T185	0	43	0	0
T186	0	49	0	0
T187	0	12	0	0
T188	0	6	0	0
T189	0	48	0	0
T190	0	39	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2825	0	0
T12	32503	18	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	21	0	0
T126	69820	0	0	0
T184	0	17	0	0
T185	0	22	0	0
T186	0	73	0	0
T187	0	5	0	0
T188	0	20	0	0
T189	0	61	0	0
T190	0	20	0	0
T191	0	8	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26905409	2775	0	0
T12	32503	14	0	0
T13	21818	0	0	0
T14	5391	0	0	0
T15	4578	0	0	0
T16	6844	0	0	0
T17	5096	0	0	0
T31	12383	0	0	0
T32	3467	0	0	0
T84	15758	0	0	0
T104	0	15	0	0
T126	69820	0	0	0
T184	0	31	0	0
T185	0	20	0	0
T186	0	52	0	0
T187	0	18	0	0
T188	0	34	0	0
T189	0	60	0	0
T190	0	25	0	0
T191	0	6	0	0