Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3351526	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

605684

1

T1

4

T2

168

T3

410

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3544330	1			T1	1		T2	416		T3	761
values[0x0]	204809	1			T1	13		T2	43		T3	120
values[0x1]	208071	1			T1	18		T2	57		T3	146

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2291021	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1666189

1

T1

5

T2

277

T3

523

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15806	1			T2	2		T3	1		T4	4
valid_sources[0x01]	19731	1			T3	5		T4	6		T5	1
valid_sources[0x02]	14689	1			T2	1		T3	6		T4	3
valid_sources[0x03]	12859	1			T2	1		T3	5		T4	1
valid_sources[0x04]	20732	1			T2	2		T3	4		T4	6
valid_sources[0x05]	12635	1			T2	1		T3	3		T4	6
valid_sources[0x06]	12329	1			T2	4		T3	2		T4	3
valid_sources[0x07]	18025	1			T3	6		T4	6		T6	3
valid_sources[0x08]	14849	1			T2	2		T3	2		T4	14
valid_sources[0x09]	12149	1			T2	3		T3	1		T5	10
valid_sources[0x0a]	12114	1			T2	5		T3	5		T4	2
valid_sources[0x0b]	15322	1			T2	8		T3	3		T4	11
valid_sources[0x0c]	12506	1			T2	3		T3	3		T4	12
valid_sources[0x0d]	36104	1			T1	32		T2	2		T3	4
valid_sources[0x0e]	16550	1			T2	1		T3	7		T15	1
valid_sources[0x0f]	13623	1			T2	5		T3	3		T5	2
valid_sources[0x10]	36119	1			T2	1		T3	10		T4	3
valid_sources[0x11]	12149	1			T2	2		T3	3		T4	2
valid_sources[0x12]	12629	1			T2	3		T3	1		T4	3
valid_sources[0x13]	14147	1			T2	2		T3	4		T4	10
valid_sources[0x14]	12238	1			T2	5		T3	7		T4	5
valid_sources[0x15]	13144	1			T3	7		T4	7		T6	2
valid_sources[0x16]	13459	1			T2	1		T3	4		T4	4
valid_sources[0x17]	15945	1			T2	1		T3	5		T4	4
valid_sources[0x18]	20567	1			T2	2		T3	2		T4	10
valid_sources[0x19]	13201	1			T3	4		T15	1		T4	6
valid_sources[0x1a]	12128	1			T2	2		T3	7		T4	1
valid_sources[0x1b]	13380	1			T2	1		T3	3		T4	10
valid_sources[0x1c]	15711	1			T2	2		T3	5		T4	1
valid_sources[0x1d]	18688	1			T2	2		T3	3		T4	5
valid_sources[0x1e]	12084	1			T2	2		T3	7		T4	12
valid_sources[0x1f]	17952	1			T2	7		T3	1		T4	9
valid_sources[0x20]	13145	1			T2	2		T3	2		T4	8
valid_sources[0x21]	14312	1			T3	2		T4	6		T6	14
valid_sources[0x22]	14704	1			T2	1		T3	3		T4	1
valid_sources[0x23]	13420	1			T2	1		T3	5		T4	3
valid_sources[0x24]	13847	1			T2	2		T3	3		T15	1
valid_sources[0x25]	14218	1			T2	2		T3	11		T4	4
valid_sources[0x26]	12624	1			T2	1		T3	4		T4	3
valid_sources[0x27]	13153	1			T2	1		T3	4		T15	1
valid_sources[0x28]	12725	1			T2	3		T3	3		T4	11
valid_sources[0x29]	13052	1			T2	2		T3	1		T4	1
valid_sources[0x2a]	13458	1			T2	1		T3	2		T4	6
valid_sources[0x2b]	13334	1			T2	2		T3	7		T4	3
valid_sources[0x2c]	16890	1			T3	2		T5	3		T6	3
valid_sources[0x2d]	12058	1			T2	3		T3	3		T4	7
valid_sources[0x2e]	12533	1			T2	1		T3	2		T15	1
valid_sources[0x2f]	12920	1			T2	4		T3	4		T4	3
valid_sources[0x30]	18295	1			T2	2		T3	5		T4	5
valid_sources[0x31]	19064	1			T2	3		T3	3		T4	9
valid_sources[0x32]	14074	1			T2	2		T3	4		T4	3
valid_sources[0x33]	13952	1			T2	1		T3	3		T4	2
valid_sources[0x34]	22903	1			T2	1		T3	4		T4	6
valid_sources[0x35]	13117	1			T2	1		T3	3		T5	5
valid_sources[0x36]	12190	1			T2	3		T3	3		T4	5
valid_sources[0x37]	12594	1			T2	3		T3	7		T4	5
valid_sources[0x38]	13982	1			T2	3		T3	8		T4	10
valid_sources[0x39]	13311	1			T3	2		T15	1		T4	2
valid_sources[0x3a]	13550	1			T2	7		T3	5		T15	4
valid_sources[0x3b]	16330	1			T2	1		T3	2		T4	7
valid_sources[0x3c]	15337	1			T2	2		T3	3		T15	1
valid_sources[0x3d]	24877	1			T3	6		T4	11		T6	4
valid_sources[0x3e]	21609	1			T3	5		T4	1		T5	6
valid_sources[0x3f]	13640	1			T2	1		T3	6		T4	9
valid_sources[0x40]	13155	1			T2	3		T3	6		T4	7
valid_sources[0x41]	14355	1			T2	2		T3	4		T4	2
valid_sources[0x42]	13020	1			T3	4		T4	10		T5	8
valid_sources[0x43]	13980	1			T2	2		T3	4		T4	3
valid_sources[0x44]	12709	1			T2	4		T3	3		T4	1
valid_sources[0x45]	12418	1			T2	4		T3	3		T4	2
valid_sources[0x46]	12816	1			T4	13		T6	7		T17	53
valid_sources[0x47]	12304	1			T2	1		T3	5		T4	1
valid_sources[0x48]	20723	1			T2	4		T3	4		T4	14
valid_sources[0x49]	14898	1			T2	1		T3	4		T4	3
valid_sources[0x4a]	15637	1			T2	1		T3	5		T4	5
valid_sources[0x4b]	12794	1			T2	1		T3	4		T4	1
valid_sources[0x4c]	12703	1			T2	2		T3	1		T4	6
valid_sources[0x4d]	14049	1			T2	2		T3	6		T4	9
valid_sources[0x4e]	12361	1			T2	3		T3	6		T4	3
valid_sources[0x4f]	14116	1			T2	1		T3	2		T4	4
valid_sources[0x50]	13702	1			T2	2		T3	8		T4	3
valid_sources[0x51]	14038	1			T2	1		T3	4		T5	7
valid_sources[0x52]	16312	1			T2	1		T3	2		T4	3
valid_sources[0x53]	13646	1			T2	1		T3	3		T4	4
valid_sources[0x54]	13133	1			T2	2		T3	1		T4	2
valid_sources[0x55]	13575	1			T2	3		T3	6		T4	9
valid_sources[0x56]	13444	1			T2	2		T3	7		T15	1
valid_sources[0x57]	14308	1			T3	5		T4	16		T5	5
valid_sources[0x58]	12313	1			T2	1		T3	1		T15	2
valid_sources[0x59]	17582	1			T2	1		T3	5		T4	18
valid_sources[0x5a]	13617	1			T2	4		T3	4		T4	5
valid_sources[0x5b]	11808	1			T2	2		T3	4		T4	2
valid_sources[0x5c]	20802	1			T3	4		T4	3		T5	2
valid_sources[0x5d]	14153	1			T2	2		T3	6		T4	12
valid_sources[0x5e]	12641	1			T2	2		T3	1		T4	11
valid_sources[0x5f]	12727	1			T3	3		T15	1		T4	1
valid_sources[0x60]	12723	1			T2	1		T3	7		T4	6
valid_sources[0x61]	12878	1			T2	3		T3	5		T4	1
valid_sources[0x62]	15834	1			T2	2		T3	3		T4	9
valid_sources[0x63]	16436	1			T2	4		T3	4		T4	4
valid_sources[0x64]	13372	1			T2	1		T3	4		T4	12
valid_sources[0x65]	12408	1			T2	3		T3	6		T4	8
valid_sources[0x66]	12449	1			T2	2		T3	4		T4	5
valid_sources[0x67]	12852	1			T3	4		T4	3		T5	5
valid_sources[0x68]	12217	1			T2	3		T3	7		T5	9
valid_sources[0x69]	15843	1			T2	4		T3	7		T4	3
valid_sources[0x6a]	13802	1			T2	1		T3	6		T15	1
valid_sources[0x6b]	12916	1			T3	6		T4	5		T5	6
valid_sources[0x6c]	14273	1			T2	1		T3	1		T4	3
valid_sources[0x6d]	12749	1			T2	1		T3	4		T4	5
valid_sources[0x6e]	12995	1			T2	1		T3	1		T15	1
valid_sources[0x6f]	14080	1			T2	3		T3	6		T4	5
valid_sources[0x70]	12641	1			T2	1		T3	10		T4	7
valid_sources[0x71]	12248	1			T2	2		T3	1		T4	6
valid_sources[0x72]	16560	1			T3	3		T4	4		T5	4
valid_sources[0x73]	54257	1			T2	1		T3	3		T4	10
valid_sources[0x74]	31353	1			T2	4		T3	2		T4	1
valid_sources[0x75]	13243	1			T2	3		T3	2		T15	1
valid_sources[0x76]	16277	1			T2	2		T3	10		T4	14
valid_sources[0x77]	14455	1			T2	1		T3	9		T4	1
valid_sources[0x78]	12470	1			T2	3		T3	14		T4	1
valid_sources[0x79]	12988	1			T2	3		T3	3		T4	6
valid_sources[0x7a]	13574	1			T2	2		T3	7		T4	7
valid_sources[0x7b]	15077	1			T2	2		T3	4		T4	16
valid_sources[0x7c]	12681	1			T2	4		T3	8		T4	7
valid_sources[0x7d]	12375	1			T2	3		T3	1		T4	11
valid_sources[0x7e]	12786	1			T2	3		T3	2		T4	5
valid_sources[0x7f]	18118	1			T2	4		T3	4		T6	8
valid_sources[0x80]	15638	1			T2	1		T3	1		T4	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

324394

1

T2

120

T3

315

T4

116

values[0x0]

all_enables

biggest_size

147870

1

T1

3

T2

30

T3

53

values[0x1]

all_enables

biggest_size

133420

1

T1

1

T2

18

T3

42