Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
21890742 |
21734149 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21890742 |
21734149 |
0 |
0 |
T1 |
1379 |
1293 |
0 |
0 |
T2 |
2290 |
2208 |
0 |
0 |
T3 |
23812 |
17205 |
0 |
0 |
T4 |
17913 |
17825 |
0 |
0 |
T5 |
3836 |
3743 |
0 |
0 |
T6 |
5232 |
5070 |
0 |
0 |
T15 |
1200 |
1123 |
0 |
0 |
T16 |
1669 |
1611 |
0 |
0 |
T17 |
166420 |
165109 |
0 |
0 |
T18 |
9137 |
9047 |
0 |
0 |