Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3311107	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

585223

1

T1

510

T2

3565

T3

172

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3499969	1			T1	613		T2	9798		T3	768
values[0x0]	197601	1			T1	165		T2	1040		T3	46
values[0x1]	198760	1			T1	145		T2	1242		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2265191	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1631139

1

T1

581

T2

6197

T3

385

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10230	1			T1	3		T2	47		T4	4
valid_sources[0x01]	10420	1			T2	43		T4	13		T5	2
valid_sources[0x02]	11835	1			T1	3		T2	56		T4	3
valid_sources[0x03]	10511	1			T1	13		T2	45		T4	2
valid_sources[0x04]	10149	1			T1	3		T2	52		T4	5
valid_sources[0x05]	10385	1			T2	54		T4	2		T5	9
valid_sources[0x06]	12363	1			T2	53		T4	5		T5	6
valid_sources[0x07]	12550	1			T1	6		T2	35		T4	7
valid_sources[0x08]	11362	1			T1	10		T2	56		T4	1
valid_sources[0x09]	11612	1			T1	18		T2	55		T3	854
valid_sources[0x0a]	12135	1			T1	7		T2	33		T4	2
valid_sources[0x0b]	14472	1			T1	8		T2	42		T4	10
valid_sources[0x0c]	10322	1			T2	42		T4	7		T5	2
valid_sources[0x0d]	10879	1			T1	1		T2	46		T4	4
valid_sources[0x0e]	11029	1			T1	4		T2	43		T4	2
valid_sources[0x0f]	10321	1			T1	1		T2	40		T4	5
valid_sources[0x10]	43002	1			T2	52		T4	3		T5	4
valid_sources[0x11]	11177	1			T1	6		T2	47		T4	3
valid_sources[0x12]	10587	1			T1	5		T2	40		T4	4
valid_sources[0x13]	15854	1			T1	6		T2	52		T4	7
valid_sources[0x14]	10756	1			T1	6		T2	44		T4	9
valid_sources[0x15]	10998	1			T1	4		T2	51		T4	3
valid_sources[0x16]	16381	1			T2	51		T4	6		T5	3
valid_sources[0x17]	34204	1			T2	35		T4	5		T5	1
valid_sources[0x18]	10515	1			T1	2		T2	54		T4	8
valid_sources[0x19]	11202	1			T1	1		T2	52		T4	6
valid_sources[0x1a]	10639	1			T1	2		T2	38		T4	3
valid_sources[0x1b]	17250	1			T1	6		T2	47		T4	4
valid_sources[0x1c]	10062	1			T1	7		T2	47		T4	7
valid_sources[0x1d]	12856	1			T1	5		T2	47		T4	2
valid_sources[0x1e]	11060	1			T1	1		T2	40		T4	2
valid_sources[0x1f]	10532	1			T1	8		T2	40		T4	8
valid_sources[0x20]	10588	1			T1	3		T2	54		T4	5
valid_sources[0x21]	9923	1			T1	9		T2	41		T4	5
valid_sources[0x22]	10285	1			T2	50		T4	7		T5	2
valid_sources[0x23]	12034	1			T1	1		T2	41		T4	10
valid_sources[0x24]	10962	1			T1	6		T2	49		T4	3
valid_sources[0x25]	11412	1			T1	2		T2	42		T4	6
valid_sources[0x26]	11258	1			T2	52		T4	6		T5	4
valid_sources[0x27]	10637	1			T1	2		T2	48		T4	4
valid_sources[0x28]	14702	1			T1	1		T2	41		T4	5
valid_sources[0x29]	10534	1			T1	2		T2	50		T4	3
valid_sources[0x2a]	11947	1			T2	53		T4	3		T5	1
valid_sources[0x2b]	10368	1			T2	41		T4	4		T5	5
valid_sources[0x2c]	11128	1			T2	44		T4	6		T5	3
valid_sources[0x2d]	12790	1			T2	49		T4	1		T5	7
valid_sources[0x2e]	9933	1			T1	9		T2	41		T4	5
valid_sources[0x2f]	10609	1			T1	4		T2	44		T4	4
valid_sources[0x30]	10751	1			T1	10		T2	48		T4	3
valid_sources[0x31]	11244	1			T2	44		T4	5		T6	3
valid_sources[0x32]	12675	1			T1	2		T2	41		T4	3
valid_sources[0x33]	10722	1			T1	3		T2	45		T4	3
valid_sources[0x34]	15656	1			T1	1		T2	50		T4	4
valid_sources[0x35]	10726	1			T1	9		T2	44		T4	5
valid_sources[0x36]	10838	1			T1	1		T2	53		T4	1
valid_sources[0x37]	15372	1			T2	53		T4	3		T5	3
valid_sources[0x38]	10273	1			T1	4		T2	46		T4	5
valid_sources[0x39]	12185	1			T1	2		T2	52		T4	5
valid_sources[0x3a]	10782	1			T1	3		T2	56		T4	1
valid_sources[0x3b]	10470	1			T1	5		T2	39		T4	4
valid_sources[0x3c]	41930	1			T1	7		T2	42		T4	10
valid_sources[0x3d]	10484	1			T2	58		T4	6		T5	1
valid_sources[0x3e]	18664	1			T1	5		T2	44		T4	4
valid_sources[0x3f]	10731	1			T1	9		T2	49		T4	7
valid_sources[0x40]	10854	1			T1	5		T2	52		T4	3
valid_sources[0x41]	22604	1			T1	5		T2	57		T4	3
valid_sources[0x42]	11749	1			T1	3		T2	56		T4	4
valid_sources[0x43]	11924	1			T1	3		T2	46		T4	6
valid_sources[0x44]	11946	1			T1	2		T2	44		T4	2
valid_sources[0x45]	11373	1			T1	2		T2	48		T4	4
valid_sources[0x46]	14456	1			T1	6		T2	44		T4	3
valid_sources[0x47]	13377	1			T1	4		T2	58		T4	6
valid_sources[0x48]	14690	1			T1	2		T2	52		T4	8
valid_sources[0x49]	10507	1			T1	2		T2	45		T4	3
valid_sources[0x4a]	10389	1			T1	5		T2	51		T4	3
valid_sources[0x4b]	10478	1			T1	3		T2	36		T4	8
valid_sources[0x4c]	12623	1			T1	6		T2	49		T4	3
valid_sources[0x4d]	9691	1			T1	5		T2	54		T4	8
valid_sources[0x4e]	10564	1			T1	4		T2	44		T4	6
valid_sources[0x4f]	20221	1			T1	4		T2	47		T4	1
valid_sources[0x50]	10063	1			T2	44		T4	6		T5	1
valid_sources[0x51]	12953	1			T1	6		T2	62		T4	7
valid_sources[0x52]	10686	1			T1	4		T2	40		T4	3
valid_sources[0x53]	10721	1			T1	11		T2	55		T4	6
valid_sources[0x54]	10731	1			T1	8		T2	41		T4	4
valid_sources[0x55]	11401	1			T1	8		T2	49		T4	9
valid_sources[0x56]	11598	1			T2	39		T4	1		T5	1
valid_sources[0x57]	13291	1			T1	1		T2	49		T4	6
valid_sources[0x58]	10689	1			T1	2		T2	43		T4	5
valid_sources[0x59]	14806	1			T1	2		T2	39		T4	7
valid_sources[0x5a]	11453	1			T1	7		T2	52		T4	2
valid_sources[0x5b]	10985	1			T1	6		T2	48		T4	4
valid_sources[0x5c]	12327	1			T1	5		T2	59		T4	3
valid_sources[0x5d]	10302	1			T1	2		T2	49		T4	6
valid_sources[0x5e]	10408	1			T1	1		T2	41		T4	4
valid_sources[0x5f]	10451	1			T1	7		T2	44		T4	7
valid_sources[0x60]	10174	1			T1	4		T2	41		T4	4
valid_sources[0x61]	11192	1			T1	7		T2	43		T4	8
valid_sources[0x62]	12751	1			T2	58		T4	2		T5	1
valid_sources[0x63]	10294	1			T1	1		T2	60		T4	8
valid_sources[0x64]	68563	1			T1	6		T2	48		T4	7
valid_sources[0x65]	21828	1			T1	4		T2	39		T4	2
valid_sources[0x66]	12194	1			T2	45		T4	4		T5	3
valid_sources[0x67]	12906	1			T1	7		T2	43		T4	7
valid_sources[0x68]	14940	1			T1	6		T2	48		T4	6
valid_sources[0x69]	10529	1			T1	3		T2	47		T4	3
valid_sources[0x6a]	10316	1			T1	9		T2	54		T4	3
valid_sources[0x6b]	115591	1			T1	4		T2	54		T4	6
valid_sources[0x6c]	24605	1			T1	2		T2	51		T4	8
valid_sources[0x6d]	10545	1			T1	1		T2	40		T4	5
valid_sources[0x6e]	10430	1			T1	2		T2	36		T4	3
valid_sources[0x6f]	10871	1			T1	3		T2	55		T5	2
valid_sources[0x70]	10302	1			T2	50		T4	6		T14	6
valid_sources[0x71]	10490	1			T2	51		T4	5		T5	1
valid_sources[0x72]	11830	1			T1	6		T2	45		T4	4
valid_sources[0x73]	10428	1			T1	4		T2	48		T4	6
valid_sources[0x74]	13030	1			T1	4		T2	47		T4	1
valid_sources[0x75]	11403	1			T1	5		T2	52		T4	3
valid_sources[0x76]	10713	1			T1	2		T2	53		T4	5
valid_sources[0x77]	10369	1			T2	38		T6	9		T15	3
valid_sources[0x78]	10173	1			T1	12		T2	44		T4	10
valid_sources[0x79]	10973	1			T2	54		T4	12		T6	19
valid_sources[0x7a]	18771	1			T1	2		T2	46		T4	4
valid_sources[0x7b]	11398	1			T2	43		T4	7		T5	2
valid_sources[0x7c]	10748	1			T1	11		T2	52		T4	5
valid_sources[0x7d]	11295	1			T2	45		T4	5		T14	2
valid_sources[0x7e]	11821	1			T1	2		T2	39		T4	7
valid_sources[0x7f]	19935	1			T1	1		T2	56		T4	3
valid_sources[0x80]	11309	1			T1	7		T2	61		T4	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

317558

1

T1

303

T2

1914

T3

144

values[0x0]

all_enables

biggest_size

141399

1

T1

113

T2

843

T3

23

values[0x1]

all_enables

biggest_size

126266

1

T1

94

T2

808

T3

5