Unified Coverage Report :: Module :: keymgr_cfg_en

Module : keymgr_cfg_en

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_cfgen	98.15	100.00	94.44			100.00
tb.dut.u_sw_binding_regwen	98.25	100.00	94.74			100.00

---

Module Instance : tb.dut.u_cfgen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.15	100.00	94.44			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.15	100.00	94.44			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sw_binding_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.25	100.00	94.74			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.25	100.00	94.74			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : keymgr_cfg_en

	Line No.	Total	Covered	Percent
TOTAL		19	19	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	38	1	1	100.00
ALWAYS	41	6	6	100.00
ALWAYS	52	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
31	1	1
32	1	1
37	1	1
38	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
			MISSING_ELSE
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE

---

Cond Coverage for Module : keymgr_cfg_en

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : keymgr_cfg_en

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
IF	41	4	4	100.00
IF	52	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))
-2-:	43	if ((init_q && (!en_i)))
-3-:	45	if ((init_i && en_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T6
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	52	if ((!rst_ni))
-2-:	54	if (vld_dis)
-3-:	56	if (vld_set)
-4-:	58	if (out_clr)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T4,T6
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cfgen

	Line No.	Total	Covered	Percent
TOTAL		19	19	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	38	1	1	100.00
ALWAYS	41	6	6	100.00
ALWAYS	52	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
31	1	1
32	1	1
37	1	1
38	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
			MISSING_ELSE
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_cfgen

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_cfgen

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
IF	41	4	4	100.00
IF	52	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))
-2-:	43	if ((init_q && (!en_i)))
-3-:	45	if ((init_i && en_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T6
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	52	if ((!rst_ni))
-2-:	54	if (vld_dis)
-3-:	56	if (vld_set)
-4-:	58	if (out_clr)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T4,T6
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sw_binding_regwen

	Line No.	Total	Covered	Percent
TOTAL		19	19	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	38	1	1	100.00
ALWAYS	41	6	6	100.00
ALWAYS	52	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
31	1	1
32	1	1
37	1	1
38	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
			MISSING_ELSE
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sw_binding_regwen

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T56,T57
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sw_binding_regwen

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
IF	41	4	4	100.00
IF	52	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))
-2-:	43	if ((init_q && (!en_i)))
-3-:	45	if ((init_i && en_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T6
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	52	if ((!rst_ni))
-2-:	54	if (vld_dis)
-3-:	56	if (vld_set)
-4-:	58	if (out_clr)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T4,T6
0	0	1	-	Covered	T2,T3,T5
0	0	0	1	Covered	T1,T2,T4
0	0	0	0	Covered	T1,T2,T3