Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
25385883 |
25214124 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25385883 |
25214124 |
0 |
0 |
T1 |
2468 |
2323 |
0 |
0 |
T2 |
39579 |
39435 |
0 |
0 |
T3 |
8934 |
8836 |
0 |
0 |
T4 |
16842 |
16785 |
0 |
0 |
T5 |
5055 |
4871 |
0 |
0 |
T6 |
2825 |
2759 |
0 |
0 |
T14 |
3031 |
2857 |
0 |
0 |
T15 |
7185 |
7085 |
0 |
0 |
T16 |
10851 |
10766 |
0 |
0 |
T17 |
1264 |
1187 |
0 |
0 |