Module Definition
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Module : keymgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.keymgr_csr_assert 100.00 100.00


Module Instance : tb.dut.keymgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : keymgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 26923550 14642 0 0
attest_sw_binding_0_rd_A 26923550 2571 0 0
attest_sw_binding_1_rd_A 26923550 2615 0 0
attest_sw_binding_2_rd_A 26923550 2665 0 0
attest_sw_binding_3_rd_A 26923550 2757 0 0
attest_sw_binding_4_rd_A 26923550 2634 0 0
attest_sw_binding_5_rd_A 26923550 2527 0 0
attest_sw_binding_6_rd_A 26923550 2638 0 0
attest_sw_binding_7_rd_A 26923550 2520 0 0
intr_enable_rd_A 26923550 3003 0 0
key_version_rd_A 26923550 2798 0 0
max_creator_key_ver_regwen_rd_A 26923550 2624 0 0
max_owner_int_key_ver_regwen_rd_A 26923550 2619 0 0
max_owner_key_ver_regwen_rd_A 26923550 2646 0 0
reseed_interval_regwen_rd_A 26923550 2708 0 0
salt_0_rd_A 26923550 2516 0 0
salt_1_rd_A 26923550 2629 0 0
salt_2_rd_A 26923550 2778 0 0
salt_3_rd_A 26923550 2572 0 0
salt_4_rd_A 26923550 2670 0 0
salt_5_rd_A 26923550 2649 0 0
salt_6_rd_A 26923550 2718 0 0
salt_7_rd_A 26923550 2673 0 0
sealing_sw_binding_0_rd_A 26923550 2599 0 0
sealing_sw_binding_1_rd_A 26923550 2473 0 0
sealing_sw_binding_2_rd_A 26923550 2582 0 0
sealing_sw_binding_3_rd_A 26923550 2698 0 0
sealing_sw_binding_4_rd_A 26923550 2691 0 0
sealing_sw_binding_5_rd_A 26923550 2636 0 0
sealing_sw_binding_6_rd_A 26923550 2745 0 0
sealing_sw_binding_7_rd_A 26923550 2591 0 0
sideload_clear_rd_A 26923550 2614 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 14642 0 0
T2 39579 1201 0 0
T3 8934 0 0 0
T4 16842 0 0 0
T5 5055 0 0 0
T6 2825 0 0 0
T14 3031 0 0 0
T15 7185 0 0 0
T16 10851 0 0 0
T17 1264 0 0 0
T39 6478 0 0 0
T71 0 172 0 0
T107 0 548 0 0
T132 0 423 0 0
T133 0 126 0 0
T134 0 281 0 0
T135 0 281 0 0
T136 0 22 0 0
T137 0 268 0 0
T138 0 390 0 0

attest_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2571 0 0
T121 0 14 0 0
T136 25703 32 0 0
T147 0 30 0 0
T150 0 4 0 0
T187 0 44 0 0
T188 0 36 0 0
T189 0 23 0 0
T190 0 16 0 0
T191 0 7 0 0
T192 0 10 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

attest_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2615 0 0
T121 0 12 0 0
T136 25703 25 0 0
T147 0 36 0 0
T150 0 9 0 0
T173 0 23 0 0
T187 0 68 0 0
T188 0 37 0 0
T189 0 29 0 0
T190 0 19 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0
T202 0 9 0 0

attest_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2665 0 0
T121 0 14 0 0
T136 25703 17 0 0
T147 0 15 0 0
T150 0 3 0 0
T173 0 35 0 0
T187 0 59 0 0
T188 0 30 0 0
T189 0 40 0 0
T190 0 21 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0
T202 0 7 0 0

attest_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2757 0 0
T121 0 14 0 0
T136 25703 26 0 0
T147 0 27 0 0
T150 0 5 0 0
T173 0 60 0 0
T187 0 43 0 0
T188 0 16 0 0
T189 0 40 0 0
T190 0 24 0 0
T192 0 9 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

attest_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2634 0 0
T121 0 17 0 0
T136 25703 31 0 0
T147 0 46 0 0
T150 0 11 0 0
T173 0 42 0 0
T187 0 49 0 0
T188 0 26 0 0
T189 0 31 0 0
T190 0 13 0 0
T191 0 2 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

attest_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2527 0 0
T121 0 17 0 0
T136 25703 27 0 0
T147 0 30 0 0
T150 0 1 0 0
T173 0 40 0 0
T187 0 52 0 0
T188 0 18 0 0
T189 0 20 0 0
T190 0 12 0 0
T192 0 1 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

attest_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2638 0 0
T121 0 16 0 0
T136 25703 26 0 0
T147 0 86 0 0
T150 0 6 0 0
T173 0 28 0 0
T187 0 47 0 0
T188 0 9 0 0
T189 0 11 0 0
T190 0 10 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0
T202 0 16 0 0

attest_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2520 0 0
T121 0 14 0 0
T136 25703 57 0 0
T147 0 3 0 0
T150 0 4 0 0
T173 0 30 0 0
T187 0 40 0 0
T188 0 41 0 0
T189 0 12 0 0
T190 0 16 0 0
T192 0 9 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 3003 0 0
T56 0 17 0 0
T136 25703 38 0 0
T187 0 87 0 0
T188 0 39 0 0
T189 0 17 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0
T203 0 35 0 0
T204 0 15 0 0
T205 0 36 0 0
T206 0 19 0 0
T207 0 12 0 0

key_version_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2798 0 0
T121 0 16 0 0
T136 25703 34 0 0
T147 0 66 0 0
T150 0 2 0 0
T187 0 45 0 0
T188 0 24 0 0
T189 0 31 0 0
T190 0 23 0 0
T191 0 4 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0
T208 0 3 0 0

max_creator_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2624 0 0
T121 0 18 0 0
T136 25703 20 0 0
T147 0 33 0 0
T150 0 8 0 0
T187 0 43 0 0
T188 0 27 0 0
T189 0 39 0 0
T190 0 10 0 0
T191 0 1 0 0
T192 0 2 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

max_owner_int_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2619 0 0
T121 0 27 0 0
T136 25703 6 0 0
T147 0 35 0 0
T150 0 12 0 0
T187 0 76 0 0
T188 0 16 0 0
T189 0 21 0 0
T190 0 17 0 0
T191 0 5 0 0
T192 0 1 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

max_owner_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2646 0 0
T121 0 19 0 0
T136 25703 31 0 0
T147 0 6 0 0
T150 0 1 0 0
T173 0 48 0 0
T187 0 60 0 0
T188 0 25 0 0
T189 0 11 0 0
T190 0 13 0 0
T191 0 12 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

reseed_interval_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2708 0 0
T121 0 12 0 0
T136 25703 31 0 0
T147 0 54 0 0
T150 0 6 0 0
T187 0 64 0 0
T188 0 35 0 0
T189 0 27 0 0
T190 0 23 0 0
T191 0 5 0 0
T192 0 12 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

salt_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2516 0 0
T121 0 10 0 0
T136 25703 13 0 0
T147 0 17 0 0
T150 0 5 0 0
T187 0 61 0 0
T188 0 40 0 0
T189 0 35 0 0
T190 0 21 0 0
T191 0 9 0 0
T192 0 2 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

salt_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2629 0 0
T121 0 22 0 0
T136 25703 40 0 0
T147 0 37 0 0
T150 0 11 0 0
T187 0 39 0 0
T188 0 20 0 0
T189 0 30 0 0
T190 0 14 0 0
T191 0 2 0 0
T192 0 21 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

salt_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2778 0 0
T121 0 17 0 0
T136 25703 27 0 0
T147 0 26 0 0
T150 0 12 0 0
T173 0 65 0 0
T187 0 65 0 0
T188 0 32 0 0
T189 0 35 0 0
T190 0 21 0 0
T191 0 1 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

salt_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2572 0 0
T121 0 14 0 0
T136 25703 16 0 0
T147 0 67 0 0
T150 0 3 0 0
T173 0 25 0 0
T187 0 70 0 0
T188 0 34 0 0
T189 0 22 0 0
T190 0 22 0 0
T192 0 3 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

salt_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2670 0 0
T121 0 26 0 0
T136 25703 33 0 0
T147 0 61 0 0
T150 0 9 0 0
T173 0 47 0 0
T187 0 68 0 0
T188 0 21 0 0
T189 0 23 0 0
T190 0 21 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0
T202 0 31 0 0

salt_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2649 0 0
T121 0 19 0 0
T136 25703 31 0 0
T147 0 34 0 0
T150 0 10 0 0
T187 0 68 0 0
T188 0 27 0 0
T189 0 16 0 0
T190 0 19 0 0
T191 0 5 0 0
T192 0 8 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

salt_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2718 0 0
T121 0 9 0 0
T136 25703 37 0 0
T147 0 29 0 0
T150 0 10 0 0
T187 0 63 0 0
T188 0 37 0 0
T189 0 22 0 0
T190 0 28 0 0
T191 0 2 0 0
T192 0 5 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

salt_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2673 0 0
T121 0 20 0 0
T136 25703 23 0 0
T147 0 54 0 0
T150 0 5 0 0
T173 0 36 0 0
T187 0 57 0 0
T188 0 36 0 0
T189 0 16 0 0
T190 0 14 0 0
T191 0 6 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

sealing_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2599 0 0
T121 0 19 0 0
T136 25703 24 0 0
T147 0 21 0 0
T150 0 11 0 0
T173 0 42 0 0
T187 0 49 0 0
T188 0 37 0 0
T189 0 41 0 0
T190 0 22 0 0
T192 0 10 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

sealing_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2473 0 0
T121 0 9 0 0
T136 25703 18 0 0
T147 0 40 0 0
T150 0 10 0 0
T187 0 51 0 0
T188 0 34 0 0
T189 0 17 0 0
T190 0 13 0 0
T191 0 3 0 0
T192 0 5 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

sealing_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2582 0 0
T121 0 20 0 0
T136 25703 32 0 0
T147 0 48 0 0
T150 0 4 0 0
T187 0 36 0 0
T188 0 15 0 0
T189 0 24 0 0
T190 0 20 0 0
T191 0 15 0 0
T192 0 11 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

sealing_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2698 0 0
T121 0 12 0 0
T136 25703 22 0 0
T147 0 58 0 0
T150 0 5 0 0
T173 0 54 0 0
T187 0 69 0 0
T188 0 14 0 0
T189 0 29 0 0
T190 0 13 0 0
T191 0 10 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

sealing_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2691 0 0
T121 0 20 0 0
T136 25703 35 0 0
T147 0 56 0 0
T150 0 3 0 0
T173 0 44 0 0
T187 0 57 0 0
T188 0 34 0 0
T189 0 28 0 0
T190 0 2 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0
T202 0 2 0 0

sealing_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2636 0 0
T121 0 21 0 0
T136 25703 26 0 0
T147 0 74 0 0
T150 0 6 0 0
T187 0 34 0 0
T188 0 47 0 0
T189 0 9 0 0
T190 0 17 0 0
T191 0 12 0 0
T192 0 3 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

sealing_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2745 0 0
T121 0 23 0 0
T136 25703 57 0 0
T147 0 53 0 0
T150 0 9 0 0
T173 0 64 0 0
T187 0 49 0 0
T188 0 33 0 0
T189 0 39 0 0
T190 0 11 0 0
T192 0 7 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

sealing_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2591 0 0
T121 0 10 0 0
T136 25703 23 0 0
T147 0 21 0 0
T150 0 8 0 0
T187 0 60 0 0
T188 0 29 0 0
T189 0 36 0 0
T190 0 16 0 0
T191 0 21 0 0
T192 0 16 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

sideload_clear_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26923550 2614 0 0
T121 0 16 0 0
T136 25703 31 0 0
T147 0 40 0 0
T150 0 6 0 0
T187 0 79 0 0
T188 0 45 0 0
T189 0 38 0 0
T190 0 16 0 0
T191 0 23 0 0
T192 0 8 0 0
T193 5020 0 0 0
T194 12071 0 0 0
T195 13177 0 0 0
T196 5914 0 0 0
T197 5905 0 0 0
T198 109779 0 0 0
T199 6522 0 0 0
T200 2558 0 0 0
T201 3829 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%