Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3433578	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

618473

1

T1

246

T2

5

T3

258

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3646428	1			T1	577		T2	1		T3	516
values[0x0]	201274	1			T1	78		T2	22		T3	62
values[0x1]	204349	1			T1	85		T2	18		T3	60

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2349034	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1703017

1

T1

353

T2

5

T3

329

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14848	1			T3	3		T6	8		T18	8
valid_sources[0x01]	13324	1			T3	3		T18	10		T19	4
valid_sources[0x02]	16028	1			T3	4		T18	9		T35	27
valid_sources[0x03]	13642	1			T3	5		T18	4		T35	58
valid_sources[0x04]	16400	1			T3	5		T6	4		T18	3
valid_sources[0x05]	12612	1			T3	2		T6	1		T18	7
valid_sources[0x06]	14244	1			T3	3		T18	5		T35	35
valid_sources[0x07]	14599	1			T3	3		T6	3		T18	12
valid_sources[0x08]	13559	1			T3	5		T18	6		T35	22
valid_sources[0x09]	15791	1			T3	2		T18	7		T19	106
valid_sources[0x0a]	13072	1			T3	1		T18	9		T19	15
valid_sources[0x0b]	17947	1			T6	1		T18	7		T35	25
valid_sources[0x0c]	13187	1			T18	7		T35	24		T36	4
valid_sources[0x0d]	13394	1			T3	1		T6	3		T18	1
valid_sources[0x0e]	14582	1			T3	7		T6	3		T18	5
valid_sources[0x0f]	15427	1			T18	3		T35	41		T36	7
valid_sources[0x10]	16364	1			T3	1		T6	1		T18	7
valid_sources[0x11]	15507	1			T3	3		T18	6		T35	35
valid_sources[0x12]	14284	1			T3	6		T18	7		T35	41
valid_sources[0x13]	13604	1			T3	2		T18	6		T35	49
valid_sources[0x14]	15568	1			T3	4		T18	5		T35	27
valid_sources[0x15]	13384	1			T3	1		T18	1		T35	29
valid_sources[0x16]	13943	1			T3	5		T6	2		T18	6
valid_sources[0x17]	17509	1			T6	1		T18	7		T35	44
valid_sources[0x18]	14215	1			T3	4		T6	1		T18	1
valid_sources[0x19]	13228	1			T3	4		T18	7		T35	23
valid_sources[0x1a]	25753	1			T3	3		T18	5		T35	26
valid_sources[0x1b]	16739	1			T3	2		T6	1		T18	4
valid_sources[0x1c]	14277	1			T3	4		T18	6		T35	29
valid_sources[0x1d]	13985	1			T3	3		T6	1		T18	8
valid_sources[0x1e]	14711	1			T3	1		T18	5		T35	31
valid_sources[0x1f]	15404	1			T3	6		T6	1		T18	12
valid_sources[0x20]	20181	1			T3	3		T18	3		T35	28
valid_sources[0x21]	12735	1			T3	4		T6	6		T18	7
valid_sources[0x22]	13506	1			T3	1		T18	7		T35	27
valid_sources[0x23]	17681	1			T6	4		T18	8		T35	53
valid_sources[0x24]	14489	1			T3	3		T6	1		T18	5
valid_sources[0x25]	13470	1			T3	2		T6	1		T18	1
valid_sources[0x26]	14930	1			T3	3		T6	4		T18	3
valid_sources[0x27]	13173	1			T18	5		T35	37		T36	5
valid_sources[0x28]	13279	1			T3	6		T6	2		T18	8
valid_sources[0x29]	15886	1			T3	3		T18	5		T19	65
valid_sources[0x2a]	15717	1			T3	6		T6	5		T18	5
valid_sources[0x2b]	14431	1			T2	41		T3	3		T6	3
valid_sources[0x2c]	13668	1			T3	2		T18	5		T35	49
valid_sources[0x2d]	22203	1			T3	1		T18	4		T35	48
valid_sources[0x2e]	15174	1			T3	7		T6	5		T35	44
valid_sources[0x2f]	13501	1			T3	3		T18	2		T35	35
valid_sources[0x30]	19259	1			T3	2		T6	3		T18	5
valid_sources[0x31]	14473	1			T3	2		T6	2		T18	3
valid_sources[0x32]	17926	1			T16	3		T18	5		T35	46
valid_sources[0x33]	14057	1			T3	4		T18	2		T35	27
valid_sources[0x34]	17134	1			T3	1		T18	1		T35	18
valid_sources[0x35]	14664	1			T3	5		T18	6		T35	27
valid_sources[0x36]	15420	1			T3	2		T6	1		T18	6
valid_sources[0x37]	14788	1			T3	1		T6	2		T18	1
valid_sources[0x38]	13302	1			T3	2		T18	6		T35	38
valid_sources[0x39]	14311	1			T3	3		T6	2		T18	11
valid_sources[0x3a]	14898	1			T6	2		T18	9		T35	55
valid_sources[0x3b]	13104	1			T18	7		T35	21		T36	3
valid_sources[0x3c]	13483	1			T6	2		T18	7		T19	1
valid_sources[0x3d]	15430	1			T3	3		T18	6		T35	31
valid_sources[0x3e]	14462	1			T18	5		T35	44		T36	5
valid_sources[0x3f]	13585	1			T3	3		T18	5		T35	25
valid_sources[0x40]	15159	1			T3	2		T18	1		T35	30
valid_sources[0x41]	16098	1			T3	4		T6	1		T18	5
valid_sources[0x42]	14005	1			T6	3		T18	6		T35	35
valid_sources[0x43]	15100	1			T1	740		T3	1		T18	7
valid_sources[0x44]	26399	1			T3	2		T6	1		T18	11
valid_sources[0x45]	15087	1			T18	7		T35	55		T36	2
valid_sources[0x46]	14611	1			T3	4		T18	8		T35	35
valid_sources[0x47]	13009	1			T3	5		T6	5		T18	3
valid_sources[0x48]	20372	1			T3	3		T6	1		T18	4
valid_sources[0x49]	17446	1			T3	4		T18	6		T35	44
valid_sources[0x4a]	17161	1			T3	2		T6	1		T18	7
valid_sources[0x4b]	14340	1			T3	3		T6	2		T18	6
valid_sources[0x4c]	16620	1			T3	1		T18	4		T19	33
valid_sources[0x4d]	16153	1			T3	5		T6	2		T18	1
valid_sources[0x4e]	13106	1			T3	1		T6	8		T18	5
valid_sources[0x4f]	12905	1			T3	3		T6	2		T18	11
valid_sources[0x50]	15521	1			T3	3		T18	8		T35	54
valid_sources[0x51]	14420	1			T3	2		T18	4		T19	4
valid_sources[0x52]	13710	1			T3	3		T18	5		T35	61
valid_sources[0x53]	12699	1			T18	2		T35	31		T36	5
valid_sources[0x54]	14055	1			T3	1		T6	6		T18	2
valid_sources[0x55]	18633	1			T3	1		T6	3		T18	5
valid_sources[0x56]	13558	1			T3	2		T6	1		T18	5
valid_sources[0x57]	13729	1			T18	6		T35	41		T36	4
valid_sources[0x58]	14121	1			T3	2		T18	4		T35	42
valid_sources[0x59]	16733	1			T6	2		T18	6		T35	41
valid_sources[0x5a]	15477	1			T3	3		T6	2		T18	7
valid_sources[0x5b]	16578	1			T3	3		T18	5		T35	34
valid_sources[0x5c]	16607	1			T3	1		T6	1		T18	2
valid_sources[0x5d]	13095	1			T18	7		T35	45		T36	7
valid_sources[0x5e]	13178	1			T3	3		T6	2		T18	9
valid_sources[0x5f]	19673	1			T18	2		T35	47		T36	4
valid_sources[0x60]	14079	1			T3	1		T18	5		T35	53
valid_sources[0x61]	16607	1			T3	1		T18	7		T35	39
valid_sources[0x62]	13971	1			T3	2		T18	7		T19	3
valid_sources[0x63]	15167	1			T3	5		T6	5		T18	3
valid_sources[0x64]	14755	1			T3	4		T18	2		T35	33
valid_sources[0x65]	16395	1			T3	1		T6	4		T18	2
valid_sources[0x66]	16077	1			T3	8		T6	1		T18	3
valid_sources[0x67]	13583	1			T3	3		T18	4		T35	52
valid_sources[0x68]	12969	1			T3	2		T18	11		T35	27
valid_sources[0x69]	18741	1			T3	3		T6	1		T16	8
valid_sources[0x6a]	14557	1			T3	1		T6	4		T18	8
valid_sources[0x6b]	13274	1			T3	2		T18	3		T19	27
valid_sources[0x6c]	35435	1			T3	4		T6	3		T18	5
valid_sources[0x6d]	30157	1			T3	6		T6	1		T18	4
valid_sources[0x6e]	12650	1			T3	2		T6	1		T18	6
valid_sources[0x6f]	12886	1			T3	2		T18	4		T19	80
valid_sources[0x70]	15698	1			T3	2		T6	6		T18	6
valid_sources[0x71]	13311	1			T3	2		T18	7		T35	53
valid_sources[0x72]	13809	1			T3	1		T6	2		T18	6
valid_sources[0x73]	15660	1			T3	1		T6	2		T18	9
valid_sources[0x74]	27509	1			T3	3		T6	3		T18	4
valid_sources[0x75]	16202	1			T3	3		T6	1		T18	5
valid_sources[0x76]	14900	1			T3	1		T18	6		T35	52
valid_sources[0x77]	14061	1			T3	7		T6	2		T18	9
valid_sources[0x78]	13975	1			T6	8		T18	8		T35	35
valid_sources[0x79]	13727	1			T3	1		T18	6		T35	60
valid_sources[0x7a]	12944	1			T3	5		T18	3		T35	35
valid_sources[0x7b]	12900	1			T3	3		T6	2		T18	5
valid_sources[0x7c]	13271	1			T3	2		T6	4		T18	2
valid_sources[0x7d]	12774	1			T3	7		T6	1		T18	6
valid_sources[0x7e]	15328	1			T6	4		T35	27		T36	3
valid_sources[0x7f]	18356	1			T3	3		T6	1		T18	1
valid_sources[0x80]	13703	1			T3	1		T6	2		T18	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

342634

1

T1

202

T2

1

T3

229

values[0x0]

all_enables

biggest_size

145192

1

T1

31

T2

3

T3

18

values[0x1]

all_enables

biggest_size

130647

1

T1

13

T2

1

T3

11