Line Coverage for Module :
keymgr_err
| Line No. | Total | Covered | Percent |
| TOTAL | | 53 | 53 | 100.00 |
| CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 75 | 1 | 1 | 100.00 |
| ALWAYS | 78 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 96 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 104 | 1 | 1 | 100.00 |
| ALWAYS | 109 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 127 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_err.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_err.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 66 |
1 |
1 |
| 71 |
1 |
1 |
| 75 |
1 |
1 |
| 78 |
1 |
1 |
| 79 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 86 |
1 |
1 |
| 89 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 97 |
1 |
1 |
| 98 |
1 |
1 |
| 99 |
1 |
1 |
| 100 |
1 |
1 |
| 101 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 104 |
1 |
1 |
| 109 |
1 |
1 |
| 110 |
1 |
1 |
| 112 |
1 |
1 |
| 115 |
1 |
1 |
| 116 |
1 |
1 |
| 117 |
1 |
1 |
| 118 |
1 |
1 |
| 119 |
1 |
1 |
| 120 |
1 |
1 |
| 121 |
1 |
1 |
| 122 |
1 |
1 |
| 125 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 132 |
1 |
1 |
| 133 |
1 |
1 |
| 134 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 141 |
1 |
1 |
| 142 |
1 |
1 |
| 143 |
1 |
1 |
| 144 |
1 |
1 |
| 145 |
1 |
1 |
| 146 |
1 |
1 |
| 147 |
1 |
1 |
| 148 |
1 |
1 |
| 149 |
1 |
1 |
| 150 |
1 |
1 |
Cond Coverage for Module :
keymgr_err
| Total | Covered | Percent |
| Conditions | 45 | 38 | 84.44 |
| Logical | 45 | 38 | 84.44 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
EXPRESSION (op_update_i | op_done_i)
-----1----- ----2----
| -1- | -2- | Status | Tests |
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T3,T4 |
LINE 71
EXPRESSION (err_vld & (invalid_op_i | disabled_i | invalid_i | ((|fault_o))))
---1--- ---------------------------2--------------------------
| -1- | -2- | Status | Tests |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 71
SUB-EXPRESSION (invalid_op_i | disabled_i | invalid_i | ((|fault_o)))
------1----- -----2---- ----3---- ------4-----
| -1- | -2- | -3- | -4- | Status | Tests |
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T6,T35,T38 |
| 0 | 0 | 1 | 0 | Covered | T17,T35,T39 |
| 0 | 1 | 0 | 0 | Covered | T1,T3,T4 |
| 1 | 0 | 0 | 0 | Covered | T1,T3,T4 |
LINE 75
EXPRESSION (err_vld & kmac_input_invalid_i)
---1--- ----------2---------
| -1- | -2- | Status | Tests |
| 0 | 1 | Covered | T5,T26,T27 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T5,T26,T27 |
LINE 92
EXPRESSION (err_vld & kmac_op_err_i)
---1--- ------2------
| -1- | -2- | Status | Tests |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T35,T40,T38 |
LINE 93
EXPRESSION (err_vld & invalid_kmac_out_i)
---1--- ---------2--------
| -1- | -2- | Status | Tests |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Not Covered | |
LINE 94
EXPRESSION (err_vld & sideload_sel_err_i)
---1--- ---------2--------
| -1- | -2- | Status | Tests |
| 0 | 1 | Covered | T39,T41,T42 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T39,T41,T42 |
LINE 121
EXPRESSION (ctrl_fsm_err_i | data_fsm_err_i | op_fsm_err_i)
-------1------ -------2------ ------3-----
| -1- | -2- | -3- | Status | Tests |
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T13,T14,T15 |
| 0 | 1 | 0 | Covered | T13,T14,T15 |
| 1 | 0 | 0 | Covered | T13,T14,T15 |
LINE 125
EXPRESSION (state_change_err_i | op_state_cmd_err_i)
---------1-------- ---------2--------
| -1- | -2- | Status | Tests |
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T10,T21,T28 |
| 1 | 0 | Not Covered | |
LINE 132
EXPRESSION (op_done_i & sync_err_o[SyncErrInvalidOp])
----1---- --------------2-------------
| -1- | -2- | Status | Tests |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 133
EXPRESSION (op_done_i & sync_err_o[SyncErrInvalidIn])
----1---- --------------2-------------
| -1- | -2- | Status | Tests |
| 0 | 1 | Covered | T23,T24,T22 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T5,T26,T27 |
LINE 137
EXPRESSION (op_done_i & sync_fault_o[SyncFaultKmacOp])
----1---- --------------2--------------
| -1- | -2- | Status | Tests |
| 0 | 1 | Covered | T38,T43,T44 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T35,T40,T38 |
LINE 138
EXPRESSION (op_done_i & sync_fault_o[SyncFaultKmacOut])
----1---- ---------------2--------------
| -1- | -2- | Status | Tests |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Not Covered | |
LINE 139
EXPRESSION (op_done_i & sync_fault_o[SyncFaultSideSel])
----1---- ---------------2--------------
| -1- | -2- | Status | Tests |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T39,T41,T42 |
Branch Coverage for Module :
keymgr_err
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
10 |
100.00 |
| IF |
78 |
4 |
4 |
100.00 |
| IF |
96 |
4 |
4 |
100.00 |
| IF |
109 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_err.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_err.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 if ((!rst_ni))
-2-: 80 if (op_done_i)
-3-: 82 if (op_update_i)
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T3,T4 |
| 0 |
0 |
1 |
Covered |
T1,T3,T4 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 96 if ((!rst_ni))
-2-: 98 if (op_done_i)
-3-: 100 if (op_update_i)
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T3,T4 |
| 0 |
0 |
1 |
Covered |
T1,T3,T4 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 109 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |