Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
24196785 |
24036183 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
24196785 |
24036183 |
0 |
0 |
T1 |
2585 |
2489 |
0 |
0 |
T2 |
1504 |
1452 |
0 |
0 |
T3 |
6694 |
6624 |
0 |
0 |
T4 |
13087 |
13001 |
0 |
0 |
T5 |
16197 |
16114 |
0 |
0 |
T6 |
4058 |
3907 |
0 |
0 |
T16 |
840 |
780 |
0 |
0 |
T17 |
4870 |
4734 |
0 |
0 |
T18 |
20717 |
20628 |
0 |
0 |
T19 |
12055 |
11851 |
0 |
0 |