Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25920939	20066	0	0
attest_sw_binding_0_rd_A	25920939	2829	0	0
attest_sw_binding_1_rd_A	25920939	2910	0	0
attest_sw_binding_2_rd_A	25920939	2943	0	0
attest_sw_binding_3_rd_A	25920939	2869	0	0
attest_sw_binding_4_rd_A	25920939	2863	0	0
attest_sw_binding_5_rd_A	25920939	2959	0	0
attest_sw_binding_6_rd_A	25920939	3052	0	0
attest_sw_binding_7_rd_A	25920939	2931	0	0
intr_enable_rd_A	25920939	3442	0	0
key_version_rd_A	25920939	2973	0	0
max_creator_key_ver_regwen_rd_A	25920939	2757	0	0
max_owner_int_key_ver_regwen_rd_A	25920939	3005	0	0
max_owner_key_ver_regwen_rd_A	25920939	3002	0	0
reseed_interval_regwen_rd_A	25920939	2949	0	0
salt_0_rd_A	25920939	2934	0	0
salt_1_rd_A	25920939	2960	0	0
salt_2_rd_A	25920939	2961	0	0
salt_3_rd_A	25920939	2956	0	0
salt_4_rd_A	25920939	3073	0	0
salt_5_rd_A	25920939	2963	0	0
salt_6_rd_A	25920939	2862	0	0
salt_7_rd_A	25920939	3072	0	0
sealing_sw_binding_0_rd_A	25920939	2964	0	0
sealing_sw_binding_1_rd_A	25920939	3068	0	0
sealing_sw_binding_2_rd_A	25920939	2941	0	0
sealing_sw_binding_3_rd_A	25920939	3028	0	0
sealing_sw_binding_4_rd_A	25920939	3020	0	0
sealing_sw_binding_5_rd_A	25920939	3113	0	0
sealing_sw_binding_6_rd_A	25920939	2889	0	0
sealing_sw_binding_7_rd_A	25920939	3015	0	0
sideload_clear_rd_A	25920939	2921	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	20066	0	0
T7	0	579	0	0
T19	12055	53	0	0
T26	4182	0	0	0
T35	39004	0	0	0
T36	7984	0	0	0
T37	11478	0	0	0
T52	2326	0	0	0
T61	0	1400	0	0
T64	0	298	0	0
T73	0	455	0	0
T94	29470	0	0	0
T95	6618	0	0	0
T112	0	486	0	0
T118	0	102	0	0
T119	2441	0	0	0
T132	0	439	0	0
T134	0	591	0	0
T135	55965	0	0	0
T136	0	1475	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2829	0	0
T59	0	23	0	0
T121	0	49	0	0
T122	0	200	0	0
T154	0	515	0	0
T173	38351	20	0	0
T174	0	27	0	0
T175	0	16	0	0
T176	0	40	0	0
T177	0	12	0	0
T178	0	6	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2910	0	0
T59	0	38	0	0
T121	0	51	0	0
T122	0	182	0	0
T154	0	475	0	0
T173	38351	34	0	0
T174	0	46	0	0
T175	0	37	0	0
T176	0	60	0	0
T177	0	7	0	0
T178	0	2	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2943	0	0
T59	0	57	0	0
T121	0	48	0	0
T144	0	4	0	0
T154	0	492	0	0
T173	38351	56	0	0
T174	0	20	0	0
T175	0	14	0	0
T176	0	67	0	0
T177	0	10	0	0
T178	0	4	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2869	0	0
T59	0	58	0	0
T121	0	33	0	0
T144	0	2	0	0
T154	0	410	0	0
T173	38351	30	0	0
T174	0	37	0	0
T175	0	20	0	0
T176	0	44	0	0
T177	0	30	0	0
T178	0	17	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2863	0	0
T59	0	56	0	0
T121	0	48	0	0
T144	0	1	0	0
T154	0	463	0	0
T173	38351	17	0	0
T174	0	5	0	0
T175	0	28	0	0
T176	0	35	0	0
T177	0	11	0	0
T178	0	10	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2959	0	0
T59	0	49	0	0
T121	0	32	0	0
T144	0	1	0	0
T154	0	483	0	0
T173	38351	36	0	0
T174	0	48	0	0
T175	0	28	0	0
T176	0	76	0	0
T177	0	4	0	0
T178	0	8	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	3052	0	0
T59	0	46	0	0
T121	0	54	0	0
T144	0	6	0	0
T154	0	502	0	0
T173	38351	32	0	0
T174	0	38	0	0
T175	0	18	0	0
T176	0	80	0	0
T177	0	8	0	0
T178	0	10	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2931	0	0
T59	0	51	0	0
T121	0	20	0	0
T144	0	5	0	0
T154	0	527	0	0
T173	38351	25	0	0
T174	0	40	0	0
T175	0	35	0	0
T176	0	40	0	0
T177	0	9	0	0
T178	0	12	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	3442	0	0
T20	6711	0	0	0
T23	9296	0	0	0
T51	100794	0	0	0
T60	107868	20	0	0
T68	86480	0	0	0
T70	0	19	0	0
T98	2746	0	0	0
T139	17204	0	0	0
T173	0	24	0	0
T174	0	69	0	0
T175	0	44	0	0
T176	0	73	0	0
T188	0	46	0	0
T189	0	18	0	0
T190	0	42	0	0
T191	0	18	0	0
T192	3651	0	0	0
T193	70755	0	0	0
T194	74489	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2973	0	0
T59	0	38	0	0
T121	0	60	0	0
T122	0	206	0	0
T154	0	580	0	0
T173	38351	24	0	0
T174	0	39	0	0
T175	0	33	0	0
T176	0	63	0	0
T177	0	6	0	0
T178	0	12	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2757	0	0
T59	0	74	0	0
T121	0	53	0	0
T144	0	5	0	0
T154	0	479	0	0
T173	38351	32	0	0
T174	0	25	0	0
T175	0	21	0	0
T176	0	62	0	0
T177	0	8	0	0
T178	0	4	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	3005	0	0
T59	0	46	0	0
T121	0	58	0	0
T144	0	3	0	0
T154	0	501	0	0
T173	38351	34	0	0
T174	0	39	0	0
T175	0	46	0	0
T176	0	69	0	0
T177	0	16	0	0
T178	0	2	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	3002	0	0
T59	0	53	0	0
T121	0	47	0	0
T122	0	177	0	0
T144	0	1	0	0
T154	0	500	0	0
T173	38351	40	0	0
T174	0	20	0	0
T175	0	21	0	0
T176	0	51	0	0
T178	0	14	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2949	0	0
T59	0	36	0	0
T121	0	42	0	0
T154	0	503	0	0
T173	38351	20	0	0
T174	0	12	0	0
T175	0	43	0	0
T176	0	64	0	0
T177	0	12	0	0
T178	0	6	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0
T195	0	3	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2934	0	0
T59	0	35	0	0
T121	0	49	0	0
T122	0	217	0	0
T154	0	510	0	0
T173	38351	11	0	0
T174	0	27	0	0
T175	0	28	0	0
T176	0	68	0	0
T177	0	5	0	0
T178	0	3	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2960	0	0
T59	0	32	0	0
T121	0	45	0	0
T144	0	5	0	0
T154	0	534	0	0
T173	38351	44	0	0
T174	0	37	0	0
T175	0	26	0	0
T176	0	57	0	0
T177	0	7	0	0
T178	0	14	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2961	0	0
T59	0	27	0	0
T121	0	63	0	0
T144	0	3	0	0
T154	0	505	0	0
T173	38351	36	0	0
T174	0	48	0	0
T175	0	23	0	0
T176	0	71	0	0
T177	0	12	0	0
T178	0	12	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2956	0	0
T59	0	59	0	0
T121	0	52	0	0
T144	0	4	0	0
T154	0	489	0	0
T173	38351	36	0	0
T174	0	46	0	0
T175	0	30	0	0
T176	0	76	0	0
T177	0	18	0	0
T178	0	13	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	3073	0	0
T59	0	57	0	0
T121	0	48	0	0
T144	0	5	0	0
T154	0	476	0	0
T173	38351	47	0	0
T174	0	58	0	0
T175	0	12	0	0
T176	0	77	0	0
T177	0	18	0	0
T178	0	11	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2963	0	0
T59	0	60	0	0
T121	0	85	0	0
T144	0	4	0	0
T154	0	480	0	0
T173	38351	34	0	0
T174	0	36	0	0
T175	0	22	0	0
T176	0	61	0	0
T177	0	3	0	0
T178	0	10	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2862	0	0
T59	0	45	0	0
T121	0	53	0	0
T144	0	8	0	0
T154	0	476	0	0
T173	38351	31	0	0
T174	0	28	0	0
T175	0	44	0	0
T176	0	48	0	0
T177	0	23	0	0
T178	0	8	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	3072	0	0
T59	0	50	0	0
T121	0	77	0	0
T154	0	474	0	0
T173	0	27	0	0
T174	0	48	0	0
T175	0	36	0	0
T176	0	73	0	0
T177	0	14	0	0
T196	4643	3	0	0
T197	0	1	0	0
T198	974	0	0	0
T199	42361	0	0	0
T200	102150	0	0	0
T201	10804	0	0	0
T202	14514	0	0	0
T203	63501	0	0	0
T204	64537	0	0	0
T205	12942	0	0	0
T206	2939	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2964	0	0
T59	0	59	0	0
T121	0	59	0	0
T144	0	2	0	0
T154	0	463	0	0
T173	38351	37	0	0
T174	0	11	0	0
T175	0	28	0	0
T176	0	50	0	0
T177	0	15	0	0
T178	0	11	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	3068	0	0
T59	0	45	0	0
T121	0	54	0	0
T154	0	514	0	0
T173	0	20	0	0
T174	0	33	0	0
T175	0	16	0	0
T176	0	64	0	0
T177	0	26	0	0
T178	0	9	0	0
T207	6078	4	0	0
T208	4333	0	0	0
T209	5594	0	0	0
T210	131472	0	0	0
T211	24274	0	0	0
T212	5595	0	0	0
T213	14453	0	0	0
T214	8516	0	0	0
T215	7546	0	0	0
T216	11061	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2941	0	0
T59	0	32	0	0
T121	0	66	0	0
T144	0	1	0	0
T154	0	531	0	0
T173	38351	21	0	0
T174	0	28	0	0
T175	0	39	0	0
T176	0	64	0	0
T177	0	9	0	0
T178	0	9	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	3028	0	0
T59	0	49	0	0
T121	0	63	0	0
T122	0	215	0	0
T154	0	447	0	0
T173	38351	44	0	0
T174	0	37	0	0
T175	0	26	0	0
T176	0	56	0	0
T177	0	11	0	0
T178	0	17	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	3020	0	0
T59	0	39	0	0
T121	0	81	0	0
T144	0	1	0	0
T154	0	509	0	0
T173	38351	46	0	0
T174	0	31	0	0
T175	0	18	0	0
T176	0	41	0	0
T177	0	12	0	0
T178	0	8	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	3113	0	0
T59	0	56	0	0
T121	0	69	0	0
T144	0	1	0	0
T154	0	531	0	0
T173	38351	15	0	0
T174	0	31	0	0
T175	0	15	0	0
T176	0	58	0	0
T177	0	23	0	0
T178	0	7	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2889	0	0
T59	0	55	0	0
T121	0	70	0	0
T144	0	3	0	0
T154	0	493	0	0
T173	38351	29	0	0
T174	0	37	0	0
T175	0	32	0	0
T176	0	60	0	0
T177	0	27	0	0
T178	0	4	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	3015	0	0
T59	0	55	0	0
T121	0	68	0	0
T144	0	1	0	0
T154	0	466	0	0
T173	38351	35	0	0
T174	0	16	0	0
T175	0	45	0	0
T176	0	56	0	0
T177	0	9	0	0
T178	0	6	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25920939	2921	0	0
T59	0	57	0	0
T121	0	33	0	0
T144	0	6	0	0
T154	0	500	0	0
T173	38351	21	0	0
T174	0	7	0	0
T175	0	39	0	0
T176	0	57	0	0
T177	0	10	0	0
T178	0	17	0	0
T179	7410	0	0	0
T180	12568	0	0	0
T181	6652	0	0	0
T182	2888	0	0	0
T183	4182	0	0	0
T184	11453	0	0	0
T185	1024	0	0	0
T186	159983	0	0	0
T187	3353	0	0	0