Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2651943	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

594933

1

T1

5

T2

206

T3

496

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2841838	1			T1	1		T2	722		T3	12496
values[0x0]	200917	1			T1	8		T2	61		T3	182
values[0x1]	204121	1			T1	9		T2	57		T3	203

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1825069	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1421807

1

T1

6

T2

375

T3

4547

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10637	1			T2	8		T3	65		T4	14
valid_sources[0x01]	11594	1			T3	49		T4	6		T15	3
valid_sources[0x02]	13471	1			T3	60		T4	31		T15	6
valid_sources[0x03]	9859	1			T2	6		T3	52		T4	16
valid_sources[0x04]	10965	1			T2	4		T3	41		T4	11
valid_sources[0x05]	11185	1			T2	4		T3	61		T4	16
valid_sources[0x06]	10542	1			T2	5		T3	46		T4	17
valid_sources[0x07]	11191	1			T2	3		T3	57		T4	20
valid_sources[0x08]	10353	1			T2	3		T3	40		T4	15
valid_sources[0x09]	13517	1			T2	1		T3	47		T4	2
valid_sources[0x0a]	14772	1			T3	54		T4	26		T15	6
valid_sources[0x0b]	17317	1			T3	63		T4	7		T15	5
valid_sources[0x0c]	20935	1			T2	1		T3	37		T4	9
valid_sources[0x0d]	10891	1			T2	5		T3	57		T4	2
valid_sources[0x0e]	13409	1			T2	1		T3	43		T4	19
valid_sources[0x0f]	11130	1			T2	12		T3	45		T4	14
valid_sources[0x10]	16982	1			T3	56		T4	6		T15	3
valid_sources[0x11]	11680	1			T3	56		T4	11		T15	6
valid_sources[0x12]	11870	1			T2	2		T3	58		T4	10
valid_sources[0x13]	10905	1			T2	3		T3	43		T4	21
valid_sources[0x14]	10647	1			T2	8		T3	42		T4	11
valid_sources[0x15]	10110	1			T2	5		T3	43		T4	7
valid_sources[0x16]	13102	1			T2	5		T3	48		T4	20
valid_sources[0x17]	13922	1			T2	8		T3	46		T4	2
valid_sources[0x18]	12482	1			T2	8		T3	51		T4	12
valid_sources[0x19]	21515	1			T2	12		T3	60		T4	23
valid_sources[0x1a]	11761	1			T3	58		T4	6		T15	4
valid_sources[0x1b]	12484	1			T2	1		T3	52		T4	6
valid_sources[0x1c]	11946	1			T2	1		T3	40		T4	21
valid_sources[0x1d]	11283	1			T2	9		T3	46		T4	23
valid_sources[0x1e]	11766	1			T3	55		T4	10		T15	5
valid_sources[0x1f]	10409	1			T2	6		T3	57		T4	5
valid_sources[0x20]	10688	1			T3	40		T4	2		T15	6
valid_sources[0x21]	9875	1			T3	52		T4	9		T15	6
valid_sources[0x22]	11295	1			T2	1		T3	55		T4	10
valid_sources[0x23]	11708	1			T2	2		T3	45		T4	20
valid_sources[0x24]	14846	1			T3	49		T4	14		T15	2
valid_sources[0x25]	10737	1			T2	3		T3	55		T4	12
valid_sources[0x26]	10849	1			T3	46		T4	5		T15	2
valid_sources[0x27]	11313	1			T1	3		T2	3		T3	56
valid_sources[0x28]	10582	1			T2	3		T3	44		T4	2
valid_sources[0x29]	10217	1			T2	7		T3	50		T4	37
valid_sources[0x2a]	10526	1			T3	51		T4	6		T15	6
valid_sources[0x2b]	10223	1			T2	2		T3	52		T4	14
valid_sources[0x2c]	11758	1			T2	5		T3	48		T4	14
valid_sources[0x2d]	10004	1			T3	70		T4	8		T15	4
valid_sources[0x2e]	11038	1			T2	1		T3	50		T4	15
valid_sources[0x2f]	11001	1			T3	41		T4	20		T15	8
valid_sources[0x30]	11301	1			T3	50		T4	13		T15	8
valid_sources[0x31]	10378	1			T3	65		T4	26		T15	5
valid_sources[0x32]	11026	1			T2	2		T3	51		T4	8
valid_sources[0x33]	10880	1			T2	6		T3	52		T4	10
valid_sources[0x34]	11201	1			T3	41		T4	12		T15	4
valid_sources[0x35]	10342	1			T2	5		T3	37		T4	13
valid_sources[0x36]	13390	1			T2	4		T3	48		T4	16
valid_sources[0x37]	10287	1			T3	47		T4	11		T15	6
valid_sources[0x38]	10582	1			T3	58		T4	12		T15	3
valid_sources[0x39]	11506	1			T2	8		T3	42		T4	42
valid_sources[0x3a]	9576	1			T2	4		T3	49		T4	20
valid_sources[0x3b]	10563	1			T3	45		T4	31		T15	4
valid_sources[0x3c]	11940	1			T2	6		T3	59		T4	9
valid_sources[0x3d]	10678	1			T2	11		T3	48		T4	12
valid_sources[0x3e]	10513	1			T3	52		T4	14		T15	3
valid_sources[0x3f]	11927	1			T3	59		T4	15		T15	3
valid_sources[0x40]	11487	1			T3	53		T4	25		T15	7
valid_sources[0x41]	10958	1			T2	4		T3	36		T4	9
valid_sources[0x42]	10286	1			T2	3		T3	58		T4	17
valid_sources[0x43]	11126	1			T3	56		T4	10		T15	10
valid_sources[0x44]	10198	1			T2	2		T3	63		T4	9
valid_sources[0x45]	12132	1			T3	62		T4	15		T15	4
valid_sources[0x46]	10669	1			T3	55		T4	13		T15	3
valid_sources[0x47]	10931	1			T2	4		T3	62		T4	10
valid_sources[0x48]	11503	1			T2	3		T3	36		T4	28
valid_sources[0x49]	10225	1			T2	4		T3	45		T4	3
valid_sources[0x4a]	11304	1			T3	45		T4	26		T15	4
valid_sources[0x4b]	10327	1			T2	1		T3	53		T4	16
valid_sources[0x4c]	10774	1			T2	5		T3	75		T4	15
valid_sources[0x4d]	10289	1			T3	29		T4	16		T15	10
valid_sources[0x4e]	11345	1			T2	5		T3	61		T4	10
valid_sources[0x4f]	11872	1			T2	2		T3	63		T4	7
valid_sources[0x50]	12849	1			T3	56		T4	22		T16	14
valid_sources[0x51]	10016	1			T2	4		T3	45		T4	18
valid_sources[0x52]	10724	1			T2	5		T3	34		T4	38
valid_sources[0x53]	13785	1			T3	54		T4	7		T15	4
valid_sources[0x54]	12506	1			T2	12		T3	55		T4	5
valid_sources[0x55]	16945	1			T3	79		T4	5		T15	4
valid_sources[0x56]	10825	1			T2	1		T3	43		T4	19
valid_sources[0x57]	10757	1			T2	1		T3	55		T4	2
valid_sources[0x58]	15656	1			T2	5		T3	52		T4	20
valid_sources[0x59]	11149	1			T2	8		T3	56		T4	2
valid_sources[0x5a]	10734	1			T2	5		T3	46		T4	28
valid_sources[0x5b]	18132	1			T2	5		T3	53		T4	27
valid_sources[0x5c]	10316	1			T2	4		T3	37		T4	10
valid_sources[0x5d]	10401	1			T3	48		T4	11		T15	5
valid_sources[0x5e]	12562	1			T3	43		T4	6		T15	4
valid_sources[0x5f]	11633	1			T2	3		T3	58		T4	10
valid_sources[0x60]	12438	1			T3	38		T4	21		T15	5
valid_sources[0x61]	10290	1			T2	2		T3	61		T4	18
valid_sources[0x62]	47892	1			T2	7		T3	49		T4	10
valid_sources[0x63]	15383	1			T2	2		T3	50		T4	8
valid_sources[0x64]	29124	1			T2	4		T3	58		T4	36
valid_sources[0x65]	10946	1			T3	61		T4	18		T15	2
valid_sources[0x66]	14340	1			T3	53		T4	10		T15	3
valid_sources[0x67]	10270	1			T3	60		T4	3		T15	2
valid_sources[0x68]	10248	1			T2	4		T3	51		T4	14
valid_sources[0x69]	9894	1			T2	1		T3	53		T4	13
valid_sources[0x6a]	10867	1			T2	7		T3	27		T4	10
valid_sources[0x6b]	9791	1			T3	44		T4	7		T15	3
valid_sources[0x6c]	11661	1			T2	6		T3	51		T4	17
valid_sources[0x6d]	10519	1			T2	12		T3	61		T4	22
valid_sources[0x6e]	11123	1			T2	4		T3	54		T4	22
valid_sources[0x6f]	15798	1			T2	1		T3	47		T4	8
valid_sources[0x70]	10679	1			T3	41		T4	13		T15	3
valid_sources[0x71]	20801	1			T2	1		T3	51		T4	28
valid_sources[0x72]	10238	1			T2	2		T3	60		T4	6
valid_sources[0x73]	12787	1			T3	56		T4	12		T15	10
valid_sources[0x74]	10656	1			T2	2		T3	51		T4	11
valid_sources[0x75]	12499	1			T3	49		T4	8		T15	5
valid_sources[0x76]	11134	1			T2	13		T3	48		T4	7
valid_sources[0x77]	11652	1			T2	3		T3	53		T4	19
valid_sources[0x78]	10808	1			T2	16		T3	55		T4	4
valid_sources[0x79]	11377	1			T2	3		T3	42		T4	9
valid_sources[0x7a]	10675	1			T2	1		T3	48		T4	35
valid_sources[0x7b]	10777	1			T2	4		T3	59		T4	8
valid_sources[0x7c]	10561	1			T3	52		T4	19		T15	6
valid_sources[0x7d]	11550	1			T3	55		T4	14		T15	7
valid_sources[0x7e]	10168	1			T2	7		T3	61		T4	1
valid_sources[0x7f]	11317	1			T3	43		T4	19		T15	6
valid_sources[0x80]	10085	1			T2	7		T3	57		T4	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

318392

1

T2

168

T3

215

T4

954

values[0x0]

all_enables

biggest_size

144980

1

T1

3

T2

25

T3

136

values[0x1]

all_enables

biggest_size

131561

1

T1

2

T2

13

T3

145