Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
18525135 |
18382770 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
18525135 |
18382770 |
0 |
0 |
T1 |
1057 |
974 |
0 |
0 |
T2 |
5307 |
5080 |
0 |
0 |
T3 |
134646 |
134554 |
0 |
0 |
T4 |
50819 |
50128 |
0 |
0 |
T5 |
2998 |
2854 |
0 |
0 |
T15 |
11417 |
11351 |
0 |
0 |
T16 |
5789 |
5710 |
0 |
0 |
T17 |
48808 |
48710 |
0 |
0 |
T18 |
23235 |
23139 |
0 |
0 |
T19 |
8198 |
8048 |
0 |
0 |