Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	20433928	16048	0	0
attest_sw_binding_0_rd_A	20433928	3847	0	0
attest_sw_binding_1_rd_A	20433928	3723	0	0
attest_sw_binding_2_rd_A	20433928	3798	0	0
attest_sw_binding_3_rd_A	20433928	3774	0	0
attest_sw_binding_4_rd_A	20433928	3973	0	0
attest_sw_binding_5_rd_A	20433928	3679	0	0
attest_sw_binding_6_rd_A	20433928	3958	0	0
attest_sw_binding_7_rd_A	20433928	3766	0	0
intr_enable_rd_A	20433928	4451	0	0
key_version_rd_A	20433928	3668	0	0
max_creator_key_ver_regwen_rd_A	20433928	3850	0	0
max_owner_int_key_ver_regwen_rd_A	20433928	3779	0	0
max_owner_key_ver_regwen_rd_A	20433928	3839	0	0
reseed_interval_regwen_rd_A	20433928	3800	0	0
salt_0_rd_A	20433928	3988	0	0
salt_1_rd_A	20433928	3957	0	0
salt_2_rd_A	20433928	3968	0	0
salt_3_rd_A	20433928	3795	0	0
salt_4_rd_A	20433928	3940	0	0
salt_5_rd_A	20433928	3707	0	0
salt_6_rd_A	20433928	3801	0	0
salt_7_rd_A	20433928	3867	0	0
sealing_sw_binding_0_rd_A	20433928	3984	0	0
sealing_sw_binding_1_rd_A	20433928	3819	0	0
sealing_sw_binding_2_rd_A	20433928	3790	0	0
sealing_sw_binding_3_rd_A	20433928	3858	0	0
sealing_sw_binding_4_rd_A	20433928	3836	0	0
sealing_sw_binding_5_rd_A	20433928	4105	0	0
sealing_sw_binding_6_rd_A	20433928	3738	0	0
sealing_sw_binding_7_rd_A	20433928	3830	0	0
sideload_clear_rd_A	20433928	3863	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	16048	0	0
T4	50819	485	0	0
T5	2998	0	0	0
T8	0	291	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	27	0	0
T46	0	1006	0	0
T58	0	1	0	0
T67	0	729	0	0
T89	21033	0	0	0
T128	0	88	0	0
T129	0	528	0	0
T130	0	253	0	0
T131	0	248	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3847	0	0
T4	50819	77	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	27	0	0
T89	21033	0	0	0
T131	0	63	0	0
T180	0	18	0	0
T189	0	25	0	0
T190	0	11	0	0
T191	0	44	0	0
T192	0	15	0	0
T193	0	34	0	0
T194	0	2	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3723	0	0
T4	50819	46	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	16	0	0
T89	21033	0	0	0
T131	0	47	0	0
T180	0	13	0	0
T189	0	42	0	0
T190	0	15	0	0
T191	0	52	0	0
T192	0	4	0	0
T193	0	28	0	0
T194	0	16	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3798	0	0
T4	50819	48	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	29	0	0
T89	21033	0	0	0
T131	0	51	0	0
T180	0	9	0	0
T189	0	21	0	0
T190	0	10	0	0
T191	0	53	0	0
T192	0	8	0	0
T193	0	22	0	0
T194	0	3	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3774	0	0
T4	50819	67	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	15	0	0
T89	21033	0	0	0
T131	0	54	0	0
T180	0	6	0	0
T189	0	33	0	0
T190	0	22	0	0
T191	0	64	0	0
T192	0	23	0	0
T193	0	34	0	0
T194	0	17	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3973	0	0
T4	50819	73	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	24	0	0
T89	21033	0	0	0
T131	0	53	0	0
T180	0	14	0	0
T189	0	21	0	0
T190	0	6	0	0
T191	0	73	0	0
T192	0	15	0	0
T193	0	32	0	0
T195	0	6	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3679	0	0
T4	50819	50	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	23	0	0
T89	21033	0	0	0
T131	0	52	0	0
T180	0	11	0	0
T189	0	36	0	0
T190	0	17	0	0
T191	0	74	0	0
T192	0	2	0	0
T193	0	26	0	0
T194	0	19	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3958	0	0
T4	50819	63	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	33	0	0
T65	0	2	0	0
T89	21033	0	0	0
T131	0	53	0	0
T180	0	9	0	0
T189	0	29	0	0
T190	0	15	0	0
T191	0	82	0	0
T192	0	10	0	0
T193	0	21	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3766	0	0
T4	50819	64	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	21	0	0
T89	21033	0	0	0
T131	0	72	0	0
T180	0	17	0	0
T189	0	28	0	0
T190	0	31	0	0
T191	0	71	0	0
T192	0	12	0	0
T193	0	17	0	0
T194	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	4451	0	0
T4	50819	105	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	12	0	0
T76	0	51	0	0
T89	21033	0	0	0
T131	0	84	0	0
T180	0	2	0	0
T189	0	32	0	0
T190	0	46	0	0
T191	0	94	0	0
T196	0	20	0	0
T197	0	14	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3668	0	0
T4	50819	43	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	26	0	0
T89	21033	0	0	0
T131	0	47	0	0
T152	0	37	0	0
T180	0	20	0	0
T189	0	35	0	0
T190	0	15	0	0
T191	0	62	0	0
T192	0	16	0	0
T193	0	26	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3850	0	0
T4	50819	49	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	14	0	0
T89	21033	0	0	0
T131	0	59	0	0
T180	0	13	0	0
T189	0	43	0	0
T190	0	14	0	0
T191	0	88	0	0
T192	0	26	0	0
T193	0	25	0	0
T194	0	21	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3779	0	0
T4	50819	66	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	32	0	0
T89	21033	0	0	0
T131	0	74	0	0
T180	0	36	0	0
T189	0	32	0	0
T190	0	8	0	0
T191	0	98	0	0
T192	0	4	0	0
T193	0	36	0	0
T198	0	2	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3839	0	0
T4	50819	80	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	16	0	0
T89	21033	0	0	0
T131	0	69	0	0
T152	0	31	0	0
T180	0	8	0	0
T189	0	20	0	0
T190	0	31	0	0
T191	0	79	0	0
T192	0	10	0	0
T193	0	12	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3800	0	0
T4	50819	62	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	12	0	0
T89	21033	0	0	0
T131	0	63	0	0
T180	0	23	0	0
T189	0	27	0	0
T190	0	21	0	0
T191	0	63	0	0
T192	0	13	0	0
T193	0	34	0	0
T194	0	17	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3988	0	0
T4	50819	77	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	19	0	0
T89	21033	0	0	0
T131	0	47	0	0
T180	0	13	0	0
T189	0	42	0	0
T190	0	20	0	0
T191	0	76	0	0
T192	0	17	0	0
T193	0	14	0	0
T194	0	3	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3957	0	0
T4	50819	59	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	32	0	0
T89	21033	0	0	0
T131	0	57	0	0
T180	0	26	0	0
T189	0	38	0	0
T190	0	35	0	0
T191	0	80	0	0
T192	0	15	0	0
T193	0	32	0	0
T194	0	11	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3968	0	0
T4	50819	80	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	30	0	0
T89	21033	0	0	0
T131	0	62	0	0
T180	0	15	0	0
T189	0	35	0	0
T190	0	31	0	0
T191	0	99	0	0
T192	0	12	0	0
T193	0	32	0	0
T194	0	19	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3795	0	0
T4	50819	59	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	21	0	0
T89	21033	0	0	0
T131	0	61	0	0
T180	0	20	0	0
T189	0	52	0	0
T190	0	6	0	0
T191	0	55	0	0
T192	0	12	0	0
T193	0	42	0	0
T194	0	14	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3940	0	0
T4	50819	62	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	23	0	0
T89	21033	0	0	0
T131	0	45	0	0
T180	0	11	0	0
T189	0	52	0	0
T190	0	14	0	0
T191	0	69	0	0
T192	0	10	0	0
T193	0	17	0	0
T194	0	5	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3707	0	0
T4	50819	79	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	27	0	0
T89	21033	0	0	0
T131	0	27	0	0
T180	0	12	0	0
T189	0	19	0	0
T190	0	9	0	0
T191	0	70	0	0
T192	0	13	0	0
T193	0	22	0	0
T194	0	17	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3801	0	0
T4	50819	66	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	24	0	0
T89	21033	0	0	0
T131	0	44	0	0
T180	0	12	0	0
T189	0	27	0	0
T190	0	33	0	0
T191	0	49	0	0
T192	0	19	0	0
T193	0	24	0	0
T194	0	10	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3867	0	0
T4	50819	70	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	28	0	0
T89	21033	0	0	0
T131	0	32	0	0
T180	0	14	0	0
T189	0	39	0	0
T190	0	21	0	0
T191	0	72	0	0
T192	0	6	0	0
T193	0	22	0	0
T194	0	18	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3984	0	0
T4	50819	77	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	23	0	0
T89	21033	0	0	0
T131	0	51	0	0
T180	0	29	0	0
T189	0	36	0	0
T190	0	10	0	0
T191	0	56	0	0
T192	0	13	0	0
T193	0	25	0	0
T194	0	17	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3819	0	0
T4	50819	70	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	11	0	0
T89	21033	0	0	0
T131	0	62	0	0
T180	0	9	0	0
T189	0	34	0	0
T190	0	10	0	0
T191	0	49	0	0
T192	0	4	0	0
T193	0	31	0	0
T194	0	45	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3790	0	0
T4	50819	61	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	18	0	0
T89	21033	0	0	0
T131	0	89	0	0
T180	0	16	0	0
T189	0	40	0	0
T190	0	10	0	0
T191	0	88	0	0
T192	0	13	0	0
T193	0	18	0	0
T194	0	8	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3858	0	0
T4	50819	50	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	35	0	0
T89	21033	0	0	0
T131	0	42	0	0
T180	0	17	0	0
T189	0	15	0	0
T190	0	7	0	0
T191	0	67	0	0
T192	0	8	0	0
T193	0	34	0	0
T194	0	10	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3836	0	0
T4	50819	48	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	27	0	0
T89	21033	0	0	0
T131	0	66	0	0
T180	0	10	0	0
T189	0	45	0	0
T190	0	7	0	0
T191	0	92	0	0
T192	0	10	0	0
T193	0	35	0	0
T194	0	11	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	4105	0	0
T4	50819	87	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	25	0	0
T89	21033	0	0	0
T131	0	59	0	0
T180	0	18	0	0
T189	0	22	0	0
T190	0	42	0	0
T191	0	56	0	0
T192	0	17	0	0
T193	0	30	0	0
T194	0	3	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3738	0	0
T4	50819	70	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	25	0	0
T89	21033	0	0	0
T131	0	47	0	0
T180	0	12	0	0
T189	0	9	0	0
T190	0	10	0	0
T191	0	74	0	0
T192	0	28	0	0
T193	0	38	0	0
T194	0	1	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3830	0	0
T4	50819	102	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	26	0	0
T89	21033	0	0	0
T131	0	54	0	0
T180	0	5	0	0
T189	0	19	0	0
T190	0	2	0	0
T191	0	71	0	0
T192	0	5	0	0
T193	0	26	0	0
T194	0	42	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20433928	3863	0	0
T4	50819	69	0	0
T5	2998	0	0	0
T15	11417	0	0	0
T16	5789	0	0	0
T17	48808	0	0	0
T18	23235	0	0	0
T19	8198	0	0	0
T34	51595	0	0	0
T42	26815	0	0	0
T43	0	23	0	0
T89	21033	0	0	0
T131	0	59	0	0
T180	0	12	0	0
T189	0	27	0	0
T190	0	16	0	0
T191	0	66	0	0
T192	0	24	0	0
T193	0	19	0	0
T194	0	17	0	0