Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3154365	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

592180

1

T1

253

T2

452

T3

5622

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3341291	1			T1	593		T2	1108		T3	8859
values[0x0]	201649	1			T1	67		T2	176		T3	1908
values[0x1]	203605	1			T1	67		T2	179		T3	1926

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2160909	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1585636

1

T1

348

T2

757

T3

7340

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16158	1			T1	6		T2	2		T3	36
valid_sources[0x01]	13984	1			T1	4		T2	11		T3	61
valid_sources[0x02]	13941	1			T1	3		T2	7		T3	51
valid_sources[0x03]	21498	1			T1	5		T2	7		T3	45
valid_sources[0x04]	10601	1			T1	3		T2	3		T3	42
valid_sources[0x05]	14446	1			T1	1		T2	5		T3	37
valid_sources[0x06]	12024	1			T1	3		T2	6		T3	60
valid_sources[0x07]	13064	1			T1	3		T2	6		T3	65
valid_sources[0x08]	12825	1			T1	4		T2	6		T3	46
valid_sources[0x09]	16611	1			T1	1		T2	6		T3	53
valid_sources[0x0a]	11701	1			T1	1		T2	5		T3	60
valid_sources[0x0b]	11485	1			T1	1		T2	3		T3	54
valid_sources[0x0c]	11486	1			T1	3		T2	4		T3	48
valid_sources[0x0d]	11878	1			T1	2		T2	3		T3	59
valid_sources[0x0e]	13131	1			T1	1		T2	9		T3	49
valid_sources[0x0f]	12003	1			T1	6		T2	7		T3	48
valid_sources[0x10]	20950	1			T1	1		T2	6		T3	44
valid_sources[0x11]	12150	1			T1	3		T2	7		T3	53
valid_sources[0x12]	10977	1			T1	1		T2	8		T3	53
valid_sources[0x13]	13509	1			T1	6		T2	6		T3	53
valid_sources[0x14]	12695	1			T1	2		T2	7		T3	44
valid_sources[0x15]	11147	1			T1	2		T2	8		T3	50
valid_sources[0x16]	12584	1			T2	2		T3	48		T11	2
valid_sources[0x17]	12462	1			T1	5		T2	1		T3	49
valid_sources[0x18]	96503	1			T1	4		T2	6		T3	53
valid_sources[0x19]	22454	1			T1	2		T2	6		T3	50
valid_sources[0x1a]	13848	1			T2	12		T3	35		T11	4
valid_sources[0x1b]	11786	1			T2	2		T3	60		T33	5
valid_sources[0x1c]	15860	1			T1	1		T2	5		T3	48
valid_sources[0x1d]	13663	1			T1	8		T2	7		T3	47
valid_sources[0x1e]	11481	1			T1	1		T2	4		T3	44
valid_sources[0x1f]	12001	1			T1	4		T2	4		T3	46
valid_sources[0x20]	11411	1			T1	2		T2	10		T3	53
valid_sources[0x21]	12413	1			T2	9		T3	50		T11	5
valid_sources[0x22]	11635	1			T1	2		T2	2		T3	56
valid_sources[0x23]	11055	1			T1	2		T2	6		T3	53
valid_sources[0x24]	13272	1			T1	5		T2	7		T3	49
valid_sources[0x25]	13703	1			T1	1		T2	11		T3	56
valid_sources[0x26]	14110	1			T1	4		T2	9		T3	63
valid_sources[0x27]	11708	1			T1	3		T2	3		T3	49
valid_sources[0x28]	13433	1			T1	2		T2	6		T3	53
valid_sources[0x29]	12949	1			T1	8		T2	6		T3	41
valid_sources[0x2a]	23071	1			T1	2		T2	9		T3	53
valid_sources[0x2b]	13594	1			T1	1		T2	6		T3	54
valid_sources[0x2c]	11637	1			T1	6		T2	5		T3	64
valid_sources[0x2d]	11325	1			T1	1		T2	2		T3	41
valid_sources[0x2e]	17735	1			T1	4		T2	8		T3	52
valid_sources[0x2f]	13748	1			T2	6		T3	56		T11	2
valid_sources[0x30]	11531	1			T1	3		T2	6		T3	41
valid_sources[0x31]	12024	1			T1	2		T2	7		T3	51
valid_sources[0x32]	11081	1			T1	3		T2	6		T3	42
valid_sources[0x33]	12743	1			T1	8		T2	5		T3	46
valid_sources[0x34]	15434	1			T1	1		T2	7		T3	41
valid_sources[0x35]	12249	1			T1	2		T2	5		T3	47
valid_sources[0x36]	11380	1			T1	5		T2	5		T3	61
valid_sources[0x37]	14681	1			T1	1		T2	8		T3	46
valid_sources[0x38]	16075	1			T1	4		T2	13		T3	48
valid_sources[0x39]	11593	1			T1	7		T2	4		T3	57
valid_sources[0x3a]	15050	1			T1	2		T2	1		T3	53
valid_sources[0x3b]	13706	1			T1	6		T2	8		T3	45
valid_sources[0x3c]	18650	1			T1	2		T2	9		T3	37
valid_sources[0x3d]	11575	1			T1	2		T2	7		T3	62
valid_sources[0x3e]	13079	1			T1	3		T2	8		T3	47
valid_sources[0x3f]	21585	1			T1	2		T2	5		T3	42
valid_sources[0x40]	15772	1			T2	7		T3	57		T11	5
valid_sources[0x41]	15424	1			T1	9		T2	9		T3	45
valid_sources[0x42]	13927	1			T1	3		T2	7		T3	44
valid_sources[0x43]	13550	1			T2	8		T3	49		T11	3
valid_sources[0x44]	11910	1			T1	5		T2	5		T3	59
valid_sources[0x45]	12123	1			T1	2		T2	5		T3	56
valid_sources[0x46]	13219	1			T2	5		T3	46		T11	3
valid_sources[0x47]	12234	1			T1	1		T2	8		T3	63
valid_sources[0x48]	12006	1			T1	6		T2	4		T3	56
valid_sources[0x49]	11333	1			T2	4		T3	58		T11	2
valid_sources[0x4a]	11054	1			T1	2		T2	4		T3	39
valid_sources[0x4b]	11364	1			T1	3		T2	3		T3	39
valid_sources[0x4c]	13626	1			T1	4		T2	8		T3	47
valid_sources[0x4d]	27180	1			T1	2		T2	5		T3	53
valid_sources[0x4e]	27494	1			T1	3		T2	3		T3	51
valid_sources[0x4f]	15905	1			T1	2		T2	8		T3	57
valid_sources[0x50]	13212	1			T1	6		T2	8		T3	54
valid_sources[0x51]	14366	1			T1	3		T2	5		T3	48
valid_sources[0x52]	11104	1			T2	3		T3	47		T11	10
valid_sources[0x53]	11344	1			T1	4		T2	8		T3	54
valid_sources[0x54]	14111	1			T1	3		T2	1		T3	46
valid_sources[0x55]	11418	1			T1	2		T2	5		T3	53
valid_sources[0x56]	13979	1			T1	2		T2	4		T3	52
valid_sources[0x57]	16468	1			T1	2		T2	6		T3	56
valid_sources[0x58]	11475	1			T1	2		T2	6		T3	47
valid_sources[0x59]	20900	1			T1	3		T2	6		T3	49
valid_sources[0x5a]	13916	1			T1	1		T2	7		T3	64
valid_sources[0x5b]	11222	1			T1	3		T2	4		T3	53
valid_sources[0x5c]	11822	1			T1	3		T2	4		T3	54
valid_sources[0x5d]	12884	1			T1	1		T2	6		T3	43
valid_sources[0x5e]	12711	1			T1	3		T2	4		T3	43
valid_sources[0x5f]	12418	1			T2	4		T3	56		T11	1
valid_sources[0x60]	13172	1			T1	3		T2	2		T3	51
valid_sources[0x61]	15621	1			T1	3		T2	2		T3	43
valid_sources[0x62]	15560	1			T1	1		T2	5		T3	44
valid_sources[0x63]	11254	1			T2	3		T3	42		T11	1
valid_sources[0x64]	11785	1			T1	2		T2	7		T3	48
valid_sources[0x65]	14137	1			T1	3		T2	7		T3	51
valid_sources[0x66]	11396	1			T1	2		T2	7		T3	54
valid_sources[0x67]	11065	1			T1	2		T2	6		T3	40
valid_sources[0x68]	14087	1			T1	3		T2	8		T3	59
valid_sources[0x69]	11856	1			T1	3		T2	4		T3	50
valid_sources[0x6a]	11653	1			T1	3		T2	2		T3	51
valid_sources[0x6b]	16204	1			T1	3		T2	7		T3	43
valid_sources[0x6c]	22046	1			T1	1		T2	5		T3	43
valid_sources[0x6d]	17931	1			T1	2		T2	4		T3	52
valid_sources[0x6e]	19581	1			T2	4		T3	43		T11	1
valid_sources[0x6f]	14449	1			T2	7		T3	49		T11	3
valid_sources[0x70]	12228	1			T1	4		T2	5		T3	56
valid_sources[0x71]	11259	1			T1	2		T2	3		T3	43
valid_sources[0x72]	44402	1			T1	2		T2	2		T3	44
valid_sources[0x73]	26643	1			T1	1		T2	9		T3	61
valid_sources[0x74]	12379	1			T1	3		T2	5		T3	43
valid_sources[0x75]	15721	1			T1	2		T2	2		T3	50
valid_sources[0x76]	11524	1			T1	7		T2	11		T3	61
valid_sources[0x77]	21293	1			T1	8		T2	3		T3	42
valid_sources[0x78]	19336	1			T1	2		T2	5		T3	46
valid_sources[0x79]	21936	1			T1	1		T2	4		T3	48
valid_sources[0x7a]	13522	1			T1	5		T2	5		T3	59
valid_sources[0x7b]	11359	1			T1	1		T2	9		T3	61
valid_sources[0x7c]	13478	1			T1	2		T2	8		T3	36
valid_sources[0x7d]	14981	1			T1	8		T2	9		T3	47
valid_sources[0x7e]	11734	1			T1	5		T2	4		T3	49
valid_sources[0x7f]	14966	1			T2	5		T3	51		T11	2
valid_sources[0x80]	11885	1			T1	1		T2	2		T3	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

318715

1

T1

211

T2

204

T3

3129

values[0x0]

all_enables

biggest_size

144075

1

T1

34

T2

128

T3

1326

values[0x1]

all_enables

biggest_size

129390

1

T1

8

T2

120

T3

1167