Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
21050239 |
20880561 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21050239 |
20880561 |
0 |
0 |
T1 |
6464 |
6392 |
0 |
0 |
T2 |
4584 |
4534 |
0 |
0 |
T3 |
157039 |
155736 |
0 |
0 |
T4 |
10737 |
10664 |
0 |
0 |
T8 |
23635 |
16818 |
0 |
0 |
T11 |
5828 |
5748 |
0 |
0 |
T12 |
7375 |
7249 |
0 |
0 |
T13 |
5969 |
5915 |
0 |
0 |
T14 |
9654 |
9590 |
0 |
0 |
T15 |
49060 |
48920 |
0 |
0 |