Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22848413	14281	0	0
attest_sw_binding_0_rd_A	22848413	2951	0	0
attest_sw_binding_1_rd_A	22848413	3036	0	0
attest_sw_binding_2_rd_A	22848413	2889	0	0
attest_sw_binding_3_rd_A	22848413	2904	0	0
attest_sw_binding_4_rd_A	22848413	2927	0	0
attest_sw_binding_5_rd_A	22848413	3096	0	0
attest_sw_binding_6_rd_A	22848413	3095	0	0
attest_sw_binding_7_rd_A	22848413	3107	0	0
intr_enable_rd_A	22848413	3630	0	0
key_version_rd_A	22848413	2982	0	0
max_creator_key_ver_regwen_rd_A	22848413	3020	0	0
max_owner_int_key_ver_regwen_rd_A	22848413	2970	0	0
max_owner_key_ver_regwen_rd_A	22848413	2985	0	0
reseed_interval_regwen_rd_A	22848413	2906	0	0
salt_0_rd_A	22848413	2983	0	0
salt_1_rd_A	22848413	2931	0	0
salt_2_rd_A	22848413	3091	0	0
salt_3_rd_A	22848413	2989	0	0
salt_4_rd_A	22848413	2885	0	0
salt_5_rd_A	22848413	3074	0	0
salt_6_rd_A	22848413	2968	0	0
salt_7_rd_A	22848413	3091	0	0
sealing_sw_binding_0_rd_A	22848413	3047	0	0
sealing_sw_binding_1_rd_A	22848413	3064	0	0
sealing_sw_binding_2_rd_A	22848413	3087	0	0
sealing_sw_binding_3_rd_A	22848413	2992	0	0
sealing_sw_binding_4_rd_A	22848413	2997	0	0
sealing_sw_binding_5_rd_A	22848413	3020	0	0
sealing_sw_binding_6_rd_A	22848413	3075	0	0
sealing_sw_binding_7_rd_A	22848413	2936	0	0
sideload_clear_rd_A	22848413	2997	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	14281	0	0
T15	49060	56	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T50	0	960	0	0
T60	0	100	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T106	0	600	0	0
T107	0	30	0	0
T108	0	161	0	0
T109	0	91	0	0
T110	0	167	0	0
T111	0	17	0	0
T112	0	593	0	0
T113	2211	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2951	0	0
T15	49060	62	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	15	0	0
T108	0	40	0	0
T113	2211	0	0	0
T158	0	30	0	0
T161	0	19	0	0
T167	0	15	0	0
T168	0	11	0	0
T169	0	208	0	0
T170	0	241	0	0
T171	0	9	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3036	0	0
T15	49060	55	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	29	0	0
T108	0	56	0	0
T113	2211	0	0	0
T158	0	63	0	0
T161	0	9	0	0
T167	0	19	0	0
T168	0	6	0	0
T169	0	250	0	0
T170	0	205	0	0
T172	0	8	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2889	0	0
T15	49060	50	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	15	0	0
T108	0	49	0	0
T113	2211	0	0	0
T161	0	16	0	0
T167	0	30	0	0
T168	0	4	0	0
T169	0	216	0	0
T170	0	203	0	0
T173	0	10	0	0
T174	0	3	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2904	0	0
T15	49060	42	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	35	0	0
T108	0	66	0	0
T113	2211	0	0	0
T158	0	34	0	0
T161	0	16	0	0
T167	0	34	0	0
T169	0	231	0	0
T170	0	198	0	0
T171	0	6	0	0
T172	0	6	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2927	0	0
T15	49060	43	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	47	0	0
T108	0	52	0	0
T113	2211	0	0	0
T158	0	46	0	0
T161	0	26	0	0
T167	0	22	0	0
T168	0	9	0	0
T169	0	246	0	0
T170	0	199	0	0
T174	0	6	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3096	0	0
T15	49060	74	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	24	0	0
T108	0	65	0	0
T113	2211	0	0	0
T158	0	29	0	0
T161	0	26	0	0
T167	0	37	0	0
T168	0	10	0	0
T169	0	227	0	0
T170	0	286	0	0
T171	0	2	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3095	0	0
T15	49060	37	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	41	0	0
T108	0	75	0	0
T113	2211	0	0	0
T158	0	53	0	0
T161	0	23	0	0
T167	0	28	0	0
T168	0	7	0	0
T169	0	244	0	0
T170	0	232	0	0
T174	0	7	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3107	0	0
T15	49060	45	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	39	0	0
T108	0	38	0	0
T113	2211	0	0	0
T158	0	35	0	0
T161	0	28	0	0
T167	0	15	0	0
T168	0	3	0	0
T169	0	247	0	0
T170	0	235	0	0
T174	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3630	0	0
T15	49060	141	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T64	0	18	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	44	0	0
T108	0	82	0	0
T113	2211	0	0	0
T115	0	2	0	0
T167	0	16	0	0
T175	0	16	0	0
T176	0	35	0	0
T177	0	28	0	0
T178	0	20	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2982	0	0
T15	49060	61	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	31	0	0
T108	0	45	0	0
T113	2211	0	0	0
T158	0	45	0	0
T161	0	19	0	0
T167	0	30	0	0
T168	0	10	0	0
T169	0	213	0	0
T170	0	220	0	0
T174	0	19	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3020	0	0
T15	49060	57	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	16	0	0
T108	0	70	0	0
T113	2211	0	0	0
T158	0	58	0	0
T161	0	26	0	0
T167	0	28	0	0
T168	0	2	0	0
T169	0	234	0	0
T170	0	249	0	0
T174	0	9	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2970	0	0
T15	49060	41	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	9	0	0
T108	0	57	0	0
T113	2211	0	0	0
T158	0	35	0	0
T161	0	9	0	0
T167	0	14	0	0
T168	0	10	0	0
T169	0	243	0	0
T170	0	255	0	0
T171	0	9	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2985	0	0
T15	49060	33	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	28	0	0
T108	0	63	0	0
T113	2211	0	0	0
T158	0	35	0	0
T161	0	21	0	0
T167	0	18	0	0
T168	0	10	0	0
T169	0	190	0	0
T170	0	189	0	0
T174	0	6	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2906	0	0
T15	49060	61	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	26	0	0
T108	0	68	0	0
T113	2211	0	0	0
T161	0	22	0	0
T167	0	33	0	0
T168	0	18	0	0
T169	0	202	0	0
T170	0	229	0	0
T174	0	2	0	0
T179	0	8	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2983	0	0
T15	49060	43	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	16	0	0
T108	0	67	0	0
T113	2211	0	0	0
T158	0	46	0	0
T161	0	29	0	0
T167	0	28	0	0
T168	0	11	0	0
T169	0	239	0	0
T170	0	187	0	0
T171	0	6	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2931	0	0
T15	49060	33	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	24	0	0
T108	0	34	0	0
T113	2211	0	0	0
T158	0	30	0	0
T161	0	46	0	0
T167	0	28	0	0
T168	0	10	0	0
T169	0	201	0	0
T170	0	230	0	0
T174	0	7	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3091	0	0
T15	49060	50	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	30	0	0
T108	0	68	0	0
T113	2211	0	0	0
T158	0	41	0	0
T161	0	23	0	0
T167	0	34	0	0
T168	0	5	0	0
T169	0	217	0	0
T170	0	173	0	0
T171	0	15	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2989	0	0
T15	49060	61	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	30	0	0
T108	0	46	0	0
T113	2211	0	0	0
T158	0	48	0	0
T161	0	17	0	0
T167	0	32	0	0
T168	0	12	0	0
T169	0	225	0	0
T170	0	206	0	0
T174	0	6	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2885	0	0
T15	49060	57	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	25	0	0
T108	0	47	0	0
T113	2211	0	0	0
T158	0	38	0	0
T161	0	13	0	0
T167	0	28	0	0
T168	0	8	0	0
T169	0	206	0	0
T170	0	209	0	0
T180	0	1	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3074	0	0
T15	49060	45	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	20	0	0
T108	0	47	0	0
T113	2211	0	0	0
T158	0	43	0	0
T161	0	19	0	0
T167	0	15	0	0
T168	0	18	0	0
T169	0	206	0	0
T170	0	261	0	0
T174	0	12	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2968	0	0
T15	49060	45	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	24	0	0
T108	0	39	0	0
T113	2211	0	0	0
T158	0	44	0	0
T161	0	15	0	0
T167	0	40	0	0
T168	0	8	0	0
T169	0	260	0	0
T170	0	188	0	0
T171	0	8	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3091	0	0
T15	49060	52	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	22	0	0
T108	0	49	0	0
T113	2211	0	0	0
T158	0	30	0	0
T161	0	17	0	0
T167	0	18	0	0
T168	0	6	0	0
T169	0	229	0	0
T170	0	229	0	0
T174	0	6	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3047	0	0
T15	49060	69	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	22	0	0
T108	0	74	0	0
T113	2211	0	0	0
T158	0	33	0	0
T161	0	24	0	0
T167	0	33	0	0
T168	0	15	0	0
T169	0	221	0	0
T170	0	240	0	0
T171	0	5	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3064	0	0
T15	49060	61	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	22	0	0
T108	0	46	0	0
T113	2211	0	0	0
T158	0	29	0	0
T161	0	43	0	0
T167	0	24	0	0
T168	0	3	0	0
T169	0	283	0	0
T170	0	213	0	0
T171	0	7	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3087	0	0
T15	49060	45	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	24	0	0
T108	0	63	0	0
T113	2211	0	0	0
T158	0	61	0	0
T161	0	31	0	0
T167	0	40	0	0
T168	0	6	0	0
T169	0	238	0	0
T170	0	206	0	0
T171	0	3	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2992	0	0
T15	49060	45	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	28	0	0
T108	0	52	0	0
T113	2211	0	0	0
T158	0	47	0	0
T161	0	17	0	0
T167	0	35	0	0
T168	0	8	0	0
T169	0	230	0	0
T170	0	202	0	0
T174	0	1	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2997	0	0
T15	49060	31	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	41	0	0
T108	0	73	0	0
T113	2211	0	0	0
T158	0	38	0	0
T161	0	23	0	0
T167	0	41	0	0
T168	0	8	0	0
T169	0	193	0	0
T170	0	210	0	0
T174	0	7	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3020	0	0
T15	49060	66	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	43	0	0
T108	0	80	0	0
T113	2211	0	0	0
T158	0	69	0	0
T161	0	13	0	0
T167	0	20	0	0
T168	0	5	0	0
T169	0	219	0	0
T170	0	219	0	0
T181	0	7	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	3075	0	0
T15	49060	48	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	11	0	0
T108	0	51	0	0
T113	2211	0	0	0
T158	0	46	0	0
T161	0	13	0	0
T167	0	27	0	0
T168	0	7	0	0
T169	0	218	0	0
T170	0	255	0	0
T174	0	24	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2936	0	0
T15	49060	53	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	29	0	0
T108	0	41	0	0
T113	2211	0	0	0
T158	0	51	0	0
T161	0	33	0	0
T167	0	17	0	0
T168	0	11	0	0
T169	0	214	0	0
T170	0	236	0	0
T174	0	10	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22848413	2997	0	0
T15	49060	47	0	0
T16	12392	0	0	0
T21	14173	0	0	0
T32	2723	0	0	0
T33	3160	0	0	0
T77	3924	0	0	0
T78	14283	0	0	0
T79	19242	0	0	0
T91	1171	0	0	0
T107	0	22	0	0
T108	0	68	0	0
T113	2211	0	0	0
T158	0	42	0	0
T161	0	12	0	0
T167	0	27	0	0
T168	0	4	0	0
T169	0	217	0	0
T170	0	222	0	0
T174	0	3	0	0