Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2717091	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

604279

1

T1

2

T2

165

T3

169

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2911353	1			T1	1		T2	3191		T3	442
values[0x0]	203324	1			T1	8		T2	49		T3	65
values[0x1]	206693	1			T1	3		T2	62		T3	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1870281	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1451089

1

T1

4

T2

1180

T3

276

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11173	1			T2	13		T3	3		T18	139
valid_sources[0x01]	12170	1			T2	18		T3	2		T18	162
valid_sources[0x02]	10267	1			T2	11		T18	153		T5	56
valid_sources[0x03]	11294	1			T2	9		T3	2		T18	135
valid_sources[0x04]	10262	1			T2	20		T3	1		T18	139
valid_sources[0x05]	12301	1			T2	8		T3	1		T18	179
valid_sources[0x06]	9848	1			T2	13		T3	13		T18	116
valid_sources[0x07]	12846	1			T2	8		T3	7		T18	74
valid_sources[0x08]	10380	1			T2	10		T3	4		T18	138
valid_sources[0x09]	9499	1			T2	10		T18	100		T5	38
valid_sources[0x0a]	12483	1			T2	12		T3	3		T18	106
valid_sources[0x0b]	11524	1			T2	17		T18	123		T5	44
valid_sources[0x0c]	10616	1			T2	12		T3	3		T18	101
valid_sources[0x0d]	20302	1			T2	9		T3	1		T18	153
valid_sources[0x0e]	10466	1			T2	10		T3	5		T18	175
valid_sources[0x0f]	9817	1			T2	13		T3	1		T18	127
valid_sources[0x10]	10526	1			T2	12		T3	1		T18	177
valid_sources[0x11]	21689	1			T2	18		T3	2		T16	574
valid_sources[0x12]	10899	1			T2	12		T3	1		T18	165
valid_sources[0x13]	11771	1			T2	16		T3	1		T18	111
valid_sources[0x14]	16533	1			T2	17		T18	179		T5	53
valid_sources[0x15]	10385	1			T2	10		T18	142		T5	58
valid_sources[0x16]	10763	1			T2	17		T3	9		T18	149
valid_sources[0x17]	22727	1			T2	9		T18	145		T5	45
valid_sources[0x18]	10651	1			T2	6		T3	3		T18	157
valid_sources[0x19]	10648	1			T2	12		T3	1		T18	152
valid_sources[0x1a]	40379	1			T2	8		T3	3		T18	113
valid_sources[0x1b]	11216	1			T2	13		T3	2		T18	147
valid_sources[0x1c]	11026	1			T2	18		T3	3		T18	108
valid_sources[0x1d]	11399	1			T1	12		T2	10		T18	115
valid_sources[0x1e]	9716	1			T2	10		T3	3		T18	96
valid_sources[0x1f]	24793	1			T2	9		T3	1		T18	172
valid_sources[0x20]	11014	1			T2	16		T3	3		T18	145
valid_sources[0x21]	9999	1			T2	4		T18	152		T5	38
valid_sources[0x22]	10122	1			T2	8		T3	10		T18	124
valid_sources[0x23]	11379	1			T2	17		T18	112		T5	41
valid_sources[0x24]	11070	1			T2	17		T18	201		T5	52
valid_sources[0x25]	13601	1			T2	14		T18	107		T5	62
valid_sources[0x26]	10690	1			T2	10		T3	1		T18	131
valid_sources[0x27]	10373	1			T2	20		T18	161		T5	48
valid_sources[0x28]	11458	1			T2	9		T3	1		T18	107
valid_sources[0x29]	9998	1			T2	14		T18	137		T5	43
valid_sources[0x2a]	11187	1			T2	11		T3	2		T18	141
valid_sources[0x2b]	12548	1			T2	9		T18	182		T5	40
valid_sources[0x2c]	11625	1			T2	14		T3	6		T18	185
valid_sources[0x2d]	26593	1			T2	8		T3	1		T18	128
valid_sources[0x2e]	10732	1			T2	10		T3	4		T18	142
valid_sources[0x2f]	10249	1			T2	13		T18	189		T5	37
valid_sources[0x30]	10634	1			T2	17		T3	1		T18	93
valid_sources[0x31]	10876	1			T2	16		T18	114		T5	44
valid_sources[0x32]	11038	1			T2	10		T3	2		T18	126
valid_sources[0x33]	15981	1			T2	17		T3	5		T18	93
valid_sources[0x34]	10377	1			T2	16		T3	1		T18	97
valid_sources[0x35]	12330	1			T2	11		T3	1		T18	150
valid_sources[0x36]	11736	1			T2	19		T3	2		T18	157
valid_sources[0x37]	12350	1			T2	15		T3	8		T18	147
valid_sources[0x38]	10564	1			T2	11		T3	3		T18	104
valid_sources[0x39]	12066	1			T2	19		T18	138		T5	42
valid_sources[0x3a]	13808	1			T2	5		T18	135		T5	53
valid_sources[0x3b]	11586	1			T2	20		T3	1		T18	89
valid_sources[0x3c]	10379	1			T2	20		T18	106		T5	50
valid_sources[0x3d]	11075	1			T2	16		T18	175		T5	48
valid_sources[0x3e]	12394	1			T2	13		T3	2		T18	137
valid_sources[0x3f]	13631	1			T2	6		T3	2		T18	164
valid_sources[0x40]	12274	1			T2	10		T18	169		T5	53
valid_sources[0x41]	10792	1			T2	15		T3	5		T18	166
valid_sources[0x42]	10663	1			T2	11		T18	153		T5	57
valid_sources[0x43]	10631	1			T2	10		T3	10		T18	167
valid_sources[0x44]	11181	1			T2	14		T3	7		T18	165
valid_sources[0x45]	16842	1			T2	9		T3	5		T18	98
valid_sources[0x46]	11800	1			T2	8		T18	172		T5	56
valid_sources[0x47]	16554	1			T2	16		T3	2		T18	118
valid_sources[0x48]	11646	1			T2	15		T18	149		T5	51
valid_sources[0x49]	12139	1			T2	20		T18	144		T5	57
valid_sources[0x4a]	11705	1			T2	9		T3	3		T18	159
valid_sources[0x4b]	29885	1			T2	4		T3	1		T18	191
valid_sources[0x4c]	12106	1			T2	17		T18	98		T5	45
valid_sources[0x4d]	10214	1			T2	18		T3	2		T18	122
valid_sources[0x4e]	12439	1			T2	15		T3	5		T18	135
valid_sources[0x4f]	52858	1			T2	16		T3	4		T18	146
valid_sources[0x50]	10923	1			T2	10		T3	4		T18	169
valid_sources[0x51]	11014	1			T2	18		T3	1		T18	113
valid_sources[0x52]	12558	1			T2	16		T3	11		T18	139
valid_sources[0x53]	10483	1			T2	19		T3	2		T18	113
valid_sources[0x54]	10945	1			T2	17		T18	186		T5	51
valid_sources[0x55]	11200	1			T2	11		T3	1		T18	117
valid_sources[0x56]	10666	1			T2	15		T3	1		T18	183
valid_sources[0x57]	11536	1			T2	7		T18	148		T5	50
valid_sources[0x58]	10428	1			T2	16		T3	6		T18	125
valid_sources[0x59]	10268	1			T2	13		T3	1		T18	116
valid_sources[0x5a]	10353	1			T2	8		T18	107		T5	54
valid_sources[0x5b]	12828	1			T2	11		T3	1		T18	160
valid_sources[0x5c]	11569	1			T2	14		T3	1		T18	118
valid_sources[0x5d]	10962	1			T2	18		T3	3		T18	145
valid_sources[0x5e]	14449	1			T2	6		T3	8		T18	89
valid_sources[0x5f]	10752	1			T2	11		T3	1		T18	126
valid_sources[0x60]	12257	1			T2	17		T3	3		T18	88
valid_sources[0x61]	11480	1			T2	14		T18	141		T5	48
valid_sources[0x62]	10930	1			T2	8		T18	149		T5	56
valid_sources[0x63]	11238	1			T2	14		T3	1		T18	127
valid_sources[0x64]	10175	1			T2	11		T3	4		T18	159
valid_sources[0x65]	18039	1			T2	12		T18	159		T5	34
valid_sources[0x66]	17666	1			T2	18		T3	1		T18	159
valid_sources[0x67]	11910	1			T2	14		T3	2		T18	169
valid_sources[0x68]	11127	1			T2	8		T3	4		T18	147
valid_sources[0x69]	10537	1			T2	15		T3	2		T18	96
valid_sources[0x6a]	10760	1			T2	16		T18	139		T5	42
valid_sources[0x6b]	10526	1			T2	14		T3	3		T18	111
valid_sources[0x6c]	14044	1			T2	9		T3	5		T18	138
valid_sources[0x6d]	10209	1			T2	10		T3	2		T18	126
valid_sources[0x6e]	11203	1			T2	15		T3	1		T18	129
valid_sources[0x6f]	11379	1			T2	6		T3	5		T18	129
valid_sources[0x70]	13136	1			T2	16		T18	170		T5	52
valid_sources[0x71]	10381	1			T2	12		T18	129		T5	46
valid_sources[0x72]	11406	1			T2	10		T18	112		T5	52
valid_sources[0x73]	12385	1			T2	7		T3	1		T18	181
valid_sources[0x74]	12833	1			T2	13		T18	141		T5	52
valid_sources[0x75]	9887	1			T2	15		T3	5		T18	133
valid_sources[0x76]	10235	1			T2	12		T3	7		T18	140
valid_sources[0x77]	63924	1			T2	13		T18	134		T5	46
valid_sources[0x78]	13059	1			T2	7		T3	1		T18	119
valid_sources[0x79]	10520	1			T2	15		T18	178		T5	43
valid_sources[0x7a]	11993	1			T2	10		T3	1		T18	100
valid_sources[0x7b]	10737	1			T2	8		T18	172		T5	41
valid_sources[0x7c]	12802	1			T2	9		T3	6		T18	132
valid_sources[0x7d]	9846	1			T2	17		T3	2		T18	196
valid_sources[0x7e]	9948	1			T2	23		T3	9		T18	179
valid_sources[0x7f]	10057	1			T2	9		T18	94		T5	53
valid_sources[0x80]	10487	1			T2	15		T3	4		T18	185

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

325468

1

T2

122

T3

90

T4

111

values[0x0]

all_enables

biggest_size

146811

1

T1

1

T2

28

T3

48

values[0x1]

all_enables

biggest_size

132000

1

T1

1

T2

15

T3

31