Line Coverage for Module :
prim_sync_reqack_data
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
93 |
1 |
1 |
153 |
|
unreachable |
156 |
|
unreachable |
159 |
|
unreachable |
160 |
|
unreachable |
162 |
|
unreachable |
Assert Coverage for Module :
prim_sync_reqack_data
Assertion Details
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19957550 |
82877 |
0 |
0 |
T2 |
13706 |
186 |
0 |
0 |
T3 |
2366 |
50 |
0 |
0 |
T4 |
11851 |
2 |
0 |
0 |
T5 |
108787 |
838 |
0 |
0 |
T16 |
2250 |
30 |
0 |
0 |
T17 |
2269 |
2 |
0 |
0 |
T18 |
154528 |
6 |
0 |
0 |
T19 |
839 |
0 |
0 |
0 |
T20 |
5866 |
26 |
0 |
0 |
T39 |
6755 |
2 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19957550 |
82862 |
0 |
0 |
T2 |
13706 |
186 |
0 |
0 |
T3 |
2366 |
50 |
0 |
0 |
T4 |
11851 |
2 |
0 |
0 |
T5 |
108787 |
838 |
0 |
0 |
T16 |
2250 |
30 |
0 |
0 |
T17 |
2269 |
2 |
0 |
0 |
T18 |
154528 |
6 |
0 |
0 |
T19 |
839 |
0 |
0 |
0 |
T20 |
5866 |
26 |
0 |
0 |
T39 |
6755 |
2 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |