Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
19957550 |
19794072 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19957550 |
19794072 |
0 |
0 |
T1 |
627 |
574 |
0 |
0 |
T2 |
13706 |
13655 |
0 |
0 |
T3 |
2366 |
2273 |
0 |
0 |
T4 |
11851 |
11767 |
0 |
0 |
T5 |
108787 |
108633 |
0 |
0 |
T16 |
2250 |
2159 |
0 |
0 |
T17 |
2269 |
2188 |
0 |
0 |
T18 |
154528 |
154441 |
0 |
0 |
T19 |
839 |
740 |
0 |
0 |
T20 |
5866 |
5749 |
0 |
0 |