Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2915306	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

619911

1

T1

147

T2

652

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3118111	1			T1	529		T2	641		T3	1
values[0x0]	206866	1			T1	44		T2	217		T3	27
values[0x1]	210240	1			T1	39		T2	218		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2002900	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1532317

1

T1

288

T2

753

T3

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15431	1			T1	1		T2	9		T6	2
valid_sources[0x01]	11773	1			T1	2		T2	1		T6	2
valid_sources[0x02]	11703	1			T1	2		T2	11		T6	4
valid_sources[0x03]	12424	1			T2	5		T6	1		T15	4
valid_sources[0x04]	12541	1			T1	6		T2	3		T6	9
valid_sources[0x05]	12843	1			T15	6		T16	17		T18	9
valid_sources[0x06]	11531	1			T1	3		T2	4		T6	2
valid_sources[0x07]	11818	1			T1	1		T2	6		T15	2
valid_sources[0x08]	15061	1			T1	8		T2	6		T6	2
valid_sources[0x09]	11974	1			T2	5		T6	2		T16	9
valid_sources[0x0a]	12339	1			T1	1		T2	5		T5	831
valid_sources[0x0b]	28677	1			T2	5		T6	2		T15	3
valid_sources[0x0c]	12327	1			T1	3		T2	1		T6	2
valid_sources[0x0d]	12282	1			T2	12		T15	4		T16	14
valid_sources[0x0e]	12910	1			T2	3		T6	7		T15	4
valid_sources[0x0f]	10828	1			T1	2		T2	5		T6	9
valid_sources[0x10]	12515	1			T1	8		T2	12		T6	3
valid_sources[0x11]	11654	1			T1	3		T2	6		T6	2
valid_sources[0x12]	11993	1			T1	1		T2	7		T6	1
valid_sources[0x13]	21728	1			T1	1		T2	5		T15	4
valid_sources[0x14]	14447	1			T1	4		T2	6		T6	7
valid_sources[0x15]	10929	1			T1	3		T2	4		T6	3
valid_sources[0x16]	11720	1			T1	1		T2	3		T6	7
valid_sources[0x17]	14130	1			T2	4		T6	1		T15	2
valid_sources[0x18]	11802	1			T2	6		T6	2		T15	3
valid_sources[0x19]	12705	1			T1	1		T2	3		T6	1
valid_sources[0x1a]	13408	1			T1	2		T2	2		T6	5
valid_sources[0x1b]	11745	1			T1	12		T2	7		T15	6
valid_sources[0x1c]	14298	1			T1	3		T2	3		T6	3
valid_sources[0x1d]	16015	1			T2	6		T6	3		T15	3
valid_sources[0x1e]	11753	1			T1	1		T2	2		T6	1
valid_sources[0x1f]	13112	1			T1	3		T2	5		T6	5
valid_sources[0x20]	30495	1			T1	3		T2	8		T6	2
valid_sources[0x21]	14150	1			T1	2		T2	5		T6	3
valid_sources[0x22]	12635	1			T2	4		T6	3		T15	1
valid_sources[0x23]	11762	1			T1	8		T2	6		T6	6
valid_sources[0x24]	12412	1			T2	6		T6	1		T15	3
valid_sources[0x25]	11775	1			T1	3		T2	1		T6	4
valid_sources[0x26]	11470	1			T2	3		T6	5		T15	2
valid_sources[0x27]	12130	1			T2	4		T6	5		T15	2
valid_sources[0x28]	11019	1			T1	3		T2	1		T6	10
valid_sources[0x29]	114745	1			T2	3		T6	3		T15	5
valid_sources[0x2a]	11499	1			T2	4		T6	4		T15	7
valid_sources[0x2b]	12557	1			T2	3		T6	1		T15	5
valid_sources[0x2c]	15348	1			T1	9		T2	2		T6	11
valid_sources[0x2d]	11564	1			T1	7		T2	8		T6	8
valid_sources[0x2e]	13565	1			T1	5		T2	6		T6	5
valid_sources[0x2f]	11328	1			T1	1		T2	8		T15	1
valid_sources[0x30]	24012	1			T1	2		T2	5		T6	1
valid_sources[0x31]	12120	1			T1	1		T2	4		T6	15
valid_sources[0x32]	12328	1			T1	2		T2	1		T15	2
valid_sources[0x33]	11529	1			T1	8		T2	7		T6	8
valid_sources[0x34]	11288	1			T1	4		T2	2		T6	10
valid_sources[0x35]	13900	1			T1	2		T2	3		T6	1
valid_sources[0x36]	21880	1			T1	3		T2	7		T6	3
valid_sources[0x37]	12181	1			T1	2		T2	6		T6	12
valid_sources[0x38]	12186	1			T2	3		T6	4		T15	1
valid_sources[0x39]	12122	1			T1	4		T2	2		T6	7
valid_sources[0x3a]	12796	1			T1	2		T2	6		T6	1
valid_sources[0x3b]	12533	1			T2	4		T6	4		T16	9
valid_sources[0x3c]	13450	1			T1	4		T2	3		T6	2
valid_sources[0x3d]	12095	1			T1	1		T2	4		T6	5
valid_sources[0x3e]	12664	1			T2	3		T6	2		T15	4
valid_sources[0x3f]	13760	1			T1	1		T2	3		T15	2
valid_sources[0x40]	11178	1			T1	3		T2	6		T6	9
valid_sources[0x41]	14018	1			T1	1		T2	5		T6	5
valid_sources[0x42]	11230	1			T1	1		T2	1		T6	4
valid_sources[0x43]	11771	1			T2	4		T6	2		T15	2
valid_sources[0x44]	17976	1			T1	2		T2	6		T6	5
valid_sources[0x45]	13506	1			T1	5		T2	4		T6	2
valid_sources[0x46]	21443	1			T1	2		T2	7		T15	3
valid_sources[0x47]	18393	1			T1	4		T2	4		T6	2
valid_sources[0x48]	11936	1			T1	4		T2	4		T6	2
valid_sources[0x49]	11255	1			T1	2		T2	4		T6	4
valid_sources[0x4a]	13816	1			T1	2		T2	4		T6	2
valid_sources[0x4b]	10764	1			T1	6		T2	4		T6	9
valid_sources[0x4c]	11687	1			T2	6		T6	6		T15	3
valid_sources[0x4d]	11636	1			T2	1		T15	6		T16	18
valid_sources[0x4e]	11645	1			T1	2		T6	3		T15	1
valid_sources[0x4f]	11479	1			T2	4		T6	2		T15	4
valid_sources[0x50]	11817	1			T1	1		T2	2		T6	2
valid_sources[0x51]	12934	1			T1	2		T2	3		T6	4
valid_sources[0x52]	12362	1			T1	3		T2	8		T6	5
valid_sources[0x53]	12278	1			T1	11		T2	7		T6	3
valid_sources[0x54]	14812	1			T1	2		T2	4		T6	2
valid_sources[0x55]	10681	1			T2	3		T6	2		T15	1
valid_sources[0x56]	11871	1			T1	3		T2	5		T6	3
valid_sources[0x57]	10585	1			T1	3		T2	4		T6	2
valid_sources[0x58]	11571	1			T1	4		T2	4		T15	5
valid_sources[0x59]	11701	1			T1	1		T2	2		T6	7
valid_sources[0x5a]	11717	1			T2	4		T6	2		T15	1
valid_sources[0x5b]	12819	1			T1	4		T2	4		T15	2
valid_sources[0x5c]	11306	1			T1	3		T2	4		T6	8
valid_sources[0x5d]	14043	1			T2	2		T6	5		T15	1
valid_sources[0x5e]	11751	1			T1	11		T2	5		T6	5
valid_sources[0x5f]	11039	1			T2	1		T6	2		T16	4
valid_sources[0x60]	22074	1			T1	2		T2	6		T6	4
valid_sources[0x61]	21166	1			T1	2		T2	6		T6	3
valid_sources[0x62]	11559	1			T2	2		T6	5		T15	2
valid_sources[0x63]	11181	1			T1	5		T2	3		T6	6
valid_sources[0x64]	10865	1			T2	6		T6	6		T15	1
valid_sources[0x65]	11033	1			T6	3		T16	6		T17	2
valid_sources[0x66]	12893	1			T1	1		T2	6		T6	3
valid_sources[0x67]	10852	1			T1	1		T2	3		T6	5
valid_sources[0x68]	17556	1			T1	2		T2	5		T6	7
valid_sources[0x69]	11720	1			T1	6		T2	4		T6	4
valid_sources[0x6a]	11001	1			T1	1		T2	2		T6	6
valid_sources[0x6b]	14911	1			T1	1		T2	7		T6	2
valid_sources[0x6c]	19099	1			T1	2		T2	6		T6	5
valid_sources[0x6d]	12209	1			T1	2		T2	6		T6	2
valid_sources[0x6e]	12366	1			T1	4		T2	5		T6	4
valid_sources[0x6f]	13554	1			T2	3		T6	4		T15	1
valid_sources[0x70]	11335	1			T1	8		T2	5		T6	4
valid_sources[0x71]	11506	1			T1	2		T2	8		T6	5
valid_sources[0x72]	12172	1			T1	3		T2	4		T6	2
valid_sources[0x73]	25806	1			T1	7		T2	6		T6	6
valid_sources[0x74]	11368	1			T1	2		T2	4		T6	1
valid_sources[0x75]	14291	1			T1	6		T2	5		T6	6
valid_sources[0x76]	28016	1			T2	4		T6	2		T16	15
valid_sources[0x77]	14241	1			T1	3		T2	2		T6	3
valid_sources[0x78]	12340	1			T2	5		T15	4		T16	14
valid_sources[0x79]	13060	1			T1	3		T2	5		T6	2
valid_sources[0x7a]	14104	1			T1	2		T2	5		T6	4
valid_sources[0x7b]	15532	1			T1	1		T2	5		T6	2
valid_sources[0x7c]	11257	1			T1	3		T2	4		T6	2
valid_sources[0x7d]	23166	1			T1	2		T2	8		T6	2
valid_sources[0x7e]	10628	1			T1	1		T2	4		T6	8
valid_sources[0x7f]	10928	1			T2	1		T6	2		T15	5
valid_sources[0x80]	12432	1			T1	1		T2	7		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

338291

1

T1

121

T2

318

T4

135

values[0x0]

all_enables

biggest_size

148419

1

T1

16

T2

170

T3

8

values[0x1]

all_enables

biggest_size

133201

1

T1

10

T2

164

T3

8