SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
80.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_errors_cgs_wrap[keymgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 15 | 3 | 12 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_csr_size_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_instr_type_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_mem_byte_access_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_mem_ro_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_mem_wo_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_tl_protocol_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
cp_unmapped_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_write_w_instr_type_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 55336 | 1 | T56 | 1 | T116 | 1297 | T66 | 1 | ||||
auto[1] | 3545 | 1 | T116 | 117 | T124 | 98 | T75 | 99 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 37667 | 1 | T56 | 1 | T116 | 876 | T66 | 1 | ||||
auto[1] | 21214 | 1 | T116 | 538 | T124 | 712 | T75 | 464 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 58881 | 0 | T56 | 1 | T116 | 1414 | T66 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 58881 | 0 | T56 | 1 | T116 | 1414 | T66 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 58881 | 0 | T56 | 1 | T116 | 1414 | T66 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
covered | 12255 | 1 | T116 | 213 | T124 | 324 | T75 | 506 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 58257 | 1 | T56 | 1 | T116 | 1390 | T66 | 1 | ||||
auto[1] | 624 | 1 | T116 | 24 | T124 | 23 | T75 | 18 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 37761 | 1 | T56 | 1 | T116 | 892 | T66 | 1 | ||||
auto[1] | 21120 | 1 | T116 | 522 | T124 | 730 | T75 | 478 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |