SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[keymgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 3587547 | 0 | T1 | 612 | T2 | 1076 | T3 | 49 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3587328 | 1 | T1 | 612 | T2 | 1076 | T3 | 49 | ||||
values[1] | 21 | 1 | T398 | 1 | T399 | 1 | T400 | 1 | ||||
values[2] | 7 | 1 | T401 | 1 | T179 | 1 | T196 | 1 | ||||
values[3] | 117 | 1 | T43 | 1 | T67 | 1 | T402 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3587342 | 1 | T1 | 612 | T2 | 1076 | T3 | 49 | ||||
values[1] | 15 | 1 | T115 | 1 | T403 | 1 | T404 | 1 | ||||
values[2] | 8 | 1 | T60 | 1 | T66 | 1 | T405 | 1 | ||||
values[3] | 97 | 1 | T61 | 1 | T406 | 1 | T407 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3587237 | 1 | T1 | 612 | T2 | 1076 | T3 | 49 | ||||
auto[TlIntgErrCmd] | 105 | 1 | T43 | 1 | T67 | 1 | T174 | 1 | ||||
auto[TlIntgErrData] | 91 | 1 | T56 | 1 | T115 | 1 | T60 | 1 | ||||
auto[TlIntgErrBoth] | 114 | 1 | T122 | 1 | T399 | 1 | T188 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |