Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : keymgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.keymgr_csr_assert 100.00 100.00


Module Instance : tb.dut.keymgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : keymgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 22197444 18657 0 0
attest_sw_binding_0_rd_A 22197444 2159 0 0
attest_sw_binding_1_rd_A 22197444 2302 0 0
attest_sw_binding_2_rd_A 22197444 2431 0 0
attest_sw_binding_3_rd_A 22197444 2218 0 0
attest_sw_binding_4_rd_A 22197444 2180 0 0
attest_sw_binding_5_rd_A 22197444 2220 0 0
attest_sw_binding_6_rd_A 22197444 2029 0 0
attest_sw_binding_7_rd_A 22197444 2140 0 0
intr_enable_rd_A 22197444 2835 0 0
key_version_rd_A 22197444 2131 0 0
max_creator_key_ver_regwen_rd_A 22197444 2160 0 0
max_owner_int_key_ver_regwen_rd_A 22197444 2027 0 0
max_owner_key_ver_regwen_rd_A 22197444 2095 0 0
reseed_interval_regwen_rd_A 22197444 2070 0 0
salt_0_rd_A 22197444 2205 0 0
salt_1_rd_A 22197444 2091 0 0
salt_2_rd_A 22197444 2244 0 0
salt_3_rd_A 22197444 2066 0 0
salt_4_rd_A 22197444 2058 0 0
salt_5_rd_A 22197444 1948 0 0
salt_6_rd_A 22197444 2109 0 0
salt_7_rd_A 22197444 2086 0 0
sealing_sw_binding_0_rd_A 22197444 2172 0 0
sealing_sw_binding_1_rd_A 22197444 2230 0 0
sealing_sw_binding_2_rd_A 22197444 2071 0 0
sealing_sw_binding_3_rd_A 22197444 2194 0 0
sealing_sw_binding_4_rd_A 22197444 2143 0 0
sealing_sw_binding_5_rd_A 22197444 2284 0 0
sealing_sw_binding_6_rd_A 22197444 2078 0 0
sealing_sw_binding_7_rd_A 22197444 2203 0 0
sideload_clear_rd_A 22197444 2042 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 18657 0 0
T8 50918 0 0 0
T52 0 77 0 0
T53 0 143 0 0
T54 0 595 0 0
T60 9481 1 0 0
T66 2983 0 0 0
T75 0 471 0 0
T116 14196 518 0 0
T124 0 496 0 0
T137 0 1304 0 0
T138 0 261 0 0
T140 11979 0 0 0
T141 13909 0 0 0
T142 16048 0 0 0
T143 6194 0 0 0
T144 3234 0 0 0
T145 3076 0 0 0
T174 0 1 0 0

attest_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2159 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T127 0 81 0 0
T128 0 31 0 0
T148 32557 25 0 0
T157 0 16 0 0
T158 0 15 0 0
T177 0 3 0 0
T200 0 24 0 0
T201 0 17 0 0
T202 0 7 0 0
T203 0 6 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0

attest_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2302 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T127 0 109 0 0
T128 0 34 0 0
T148 32557 51 0 0
T158 0 17 0 0
T177 0 7 0 0
T200 0 41 0 0
T201 0 16 0 0
T202 0 14 0 0
T203 0 2 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 6 0 0

attest_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2431 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 27 0 0
T148 32557 61 0 0
T157 0 17 0 0
T158 0 45 0 0
T177 0 6 0 0
T200 0 25 0 0
T201 0 9 0 0
T202 0 6 0 0
T203 0 5 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 6 0 0

attest_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2218 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 34 0 0
T148 32557 45 0 0
T157 0 36 0 0
T158 0 1 0 0
T177 0 17 0 0
T200 0 21 0 0
T201 0 9 0 0
T202 0 12 0 0
T203 0 9 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 7 0 0

attest_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2180 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T127 0 96 0 0
T128 0 25 0 0
T148 32557 45 0 0
T158 0 16 0 0
T177 0 11 0 0
T200 0 37 0 0
T201 0 7 0 0
T202 0 9 0 0
T203 0 15 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 8 0 0

attest_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2220 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 26 0 0
T148 32557 61 0 0
T157 0 14 0 0
T158 0 38 0 0
T177 0 3 0 0
T200 0 20 0 0
T201 0 26 0 0
T202 0 9 0 0
T203 0 8 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 7 0 0

attest_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2029 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 24 0 0
T148 32557 33 0 0
T157 0 4 0 0
T158 0 21 0 0
T177 0 11 0 0
T200 0 20 0 0
T201 0 6 0 0
T202 0 10 0 0
T203 0 12 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 3 0 0

attest_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2140 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 19 0 0
T148 32557 22 0 0
T157 0 12 0 0
T158 0 11 0 0
T177 0 11 0 0
T200 0 44 0 0
T201 0 25 0 0
T202 0 8 0 0
T203 0 10 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 5 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2835 0 0
T7 531557 36 0 0
T56 52940 0 0 0
T58 11247 0 0 0
T62 143475 27 0 0
T64 0 16 0 0
T78 0 53 0 0
T120 0 33 0 0
T148 0 48 0 0
T154 5281 0 0 0
T200 0 30 0 0
T212 0 140 0 0
T213 0 15 0 0
T214 0 38 0 0
T215 14354 0 0 0
T216 10745 0 0 0
T217 22156 0 0 0
T218 6060 0 0 0
T219 1367 0 0 0

key_version_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2131 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 46 0 0
T148 32557 38 0 0
T157 0 41 0 0
T158 0 33 0 0
T177 0 7 0 0
T200 0 8 0 0
T201 0 13 0 0
T202 0 6 0 0
T203 0 6 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 5 0 0

max_creator_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2160 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T127 0 118 0 0
T128 0 30 0 0
T148 32557 37 0 0
T157 0 24 0 0
T158 0 16 0 0
T177 0 7 0 0
T200 0 17 0 0
T201 0 17 0 0
T203 0 13 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 7 0 0

max_owner_int_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2027 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T127 0 81 0 0
T128 0 28 0 0
T148 32557 26 0 0
T157 0 5 0 0
T158 0 18 0 0
T177 0 9 0 0
T200 0 31 0 0
T201 0 2 0 0
T202 0 4 0 0
T203 0 7 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0

max_owner_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2095 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 21 0 0
T148 32557 23 0 0
T157 0 27 0 0
T158 0 21 0 0
T177 0 11 0 0
T200 0 28 0 0
T201 0 13 0 0
T202 0 14 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 2 0 0
T220 0 1 0 0

reseed_interval_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2070 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 26 0 0
T148 32557 47 0 0
T157 0 5 0 0
T158 0 21 0 0
T177 0 9 0 0
T200 0 25 0 0
T201 0 8 0 0
T202 0 4 0 0
T203 0 23 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 2 0 0

salt_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2205 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T127 0 121 0 0
T128 0 39 0 0
T148 32557 27 0 0
T157 0 33 0 0
T158 0 29 0 0
T177 0 1 0 0
T200 0 25 0 0
T201 0 26 0 0
T202 0 11 0 0
T203 0 5 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0

salt_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2091 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 16 0 0
T148 32557 33 0 0
T157 0 36 0 0
T158 0 18 0 0
T177 0 9 0 0
T200 0 25 0 0
T201 0 24 0 0
T202 0 14 0 0
T203 0 10 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 6 0 0

salt_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2244 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T127 0 108 0 0
T128 0 29 0 0
T148 32557 56 0 0
T157 0 37 0 0
T158 0 22 0 0
T177 0 16 0 0
T200 0 40 0 0
T201 0 6 0 0
T202 0 10 0 0
T203 0 7 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0

salt_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2066 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T127 0 119 0 0
T128 0 27 0 0
T148 32557 40 0 0
T157 0 28 0 0
T158 0 31 0 0
T177 0 9 0 0
T200 0 11 0 0
T201 0 31 0 0
T202 0 19 0 0
T203 0 6 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0

salt_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2058 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 24 0 0
T148 32557 59 0 0
T157 0 41 0 0
T158 0 27 0 0
T177 0 16 0 0
T200 0 7 0 0
T201 0 12 0 0
T202 0 13 0 0
T203 0 6 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 1 0 0

salt_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 1948 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 25 0 0
T148 32557 24 0 0
T157 0 30 0 0
T158 0 19 0 0
T177 0 15 0 0
T200 0 26 0 0
T201 0 10 0 0
T202 0 5 0 0
T203 0 6 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 3 0 0

salt_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2109 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 31 0 0
T148 32557 29 0 0
T157 0 11 0 0
T158 0 46 0 0
T177 0 3 0 0
T200 0 27 0 0
T201 0 4 0 0
T202 0 8 0 0
T203 0 2 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 5 0 0

salt_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2086 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T127 0 115 0 0
T128 0 18 0 0
T148 32557 43 0 0
T157 0 15 0 0
T158 0 20 0 0
T177 0 4 0 0
T200 0 16 0 0
T201 0 19 0 0
T202 0 9 0 0
T203 0 4 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0

sealing_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2172 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 25 0 0
T148 32557 36 0 0
T157 0 10 0 0
T158 0 9 0 0
T177 0 15 0 0
T200 0 13 0 0
T201 0 8 0 0
T202 0 4 0 0
T203 0 10 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 10 0 0

sealing_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2230 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 39 0 0
T148 32557 17 0 0
T157 0 21 0 0
T158 0 29 0 0
T177 0 8 0 0
T200 0 20 0 0
T201 0 17 0 0
T202 0 8 0 0
T203 0 11 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 7 0 0

sealing_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2071 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T127 0 98 0 0
T128 0 24 0 0
T148 32557 20 0 0
T157 0 10 0 0
T158 0 9 0 0
T177 0 13 0 0
T200 0 31 0 0
T201 0 9 0 0
T202 0 7 0 0
T203 0 4 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0

sealing_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2194 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 40 0 0
T148 32557 50 0 0
T157 0 13 0 0
T158 0 35 0 0
T177 0 10 0 0
T200 0 32 0 0
T201 0 4 0 0
T202 0 13 0 0
T203 0 10 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 12 0 0

sealing_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2143 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 27 0 0
T148 32557 40 0 0
T157 0 33 0 0
T158 0 31 0 0
T177 0 2 0 0
T200 0 11 0 0
T201 0 8 0 0
T202 0 9 0 0
T203 0 15 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 12 0 0

sealing_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2284 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 32 0 0
T148 32557 25 0 0
T157 0 40 0 0
T158 0 27 0 0
T177 0 8 0 0
T200 0 17 0 0
T201 0 9 0 0
T202 0 7 0 0
T203 0 7 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 7 0 0

sealing_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2078 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 28 0 0
T148 32557 15 0 0
T157 0 11 0 0
T158 0 19 0 0
T177 0 13 0 0
T200 0 32 0 0
T201 0 31 0 0
T202 0 27 0 0
T203 0 3 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 3 0 0

sealing_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2203 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 38 0 0
T148 32557 36 0 0
T157 0 33 0 0
T158 0 33 0 0
T177 0 13 0 0
T200 0 37 0 0
T201 0 16 0 0
T202 0 14 0 0
T203 0 6 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 11 0 0

sideload_clear_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22197444 2042 0 0
T79 6184 0 0 0
T106 17370 0 0 0
T128 0 30 0 0
T148 32557 31 0 0
T157 0 27 0 0
T158 0 16 0 0
T177 0 16 0 0
T200 0 19 0 0
T201 0 17 0 0
T202 0 19 0 0
T203 0 5 0 0
T204 7007 0 0 0
T205 16034 0 0 0
T206 5829 0 0 0
T207 21504 0 0 0
T208 26897 0 0 0
T209 3694 0 0 0
T210 7812 0 0 0
T211 0 11 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%