Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2827866	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

641871

1

T1

588

T2

429

T3

271

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3038133	1			T1	11202		T2	1351		T3	223
values[0x0]	214317	1			T1	260		T2	155		T3	137
values[0x1]	217287	1			T1	231		T2	136		T3	131

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1945216	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1524521

1

T1

4258

T2

777

T3

316

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11508	1			T2	2		T15	10		T16	5
valid_sources[0x01]	10860	1			T2	3		T15	6		T16	2
valid_sources[0x02]	11750	1			T2	7		T3	3		T15	9
valid_sources[0x03]	10981	1			T2	16		T3	1		T15	11
valid_sources[0x04]	11448	1			T2	3		T3	3		T15	16
valid_sources[0x05]	12252	1			T1	42		T2	11		T3	4
valid_sources[0x06]	18649	1			T2	2		T3	2		T15	14
valid_sources[0x07]	11086	1			T3	1		T15	14		T16	4
valid_sources[0x08]	15994	1			T1	1		T2	3		T3	3
valid_sources[0x09]	12342	1			T3	2		T15	14		T16	9
valid_sources[0x0a]	11175	1			T2	7		T3	4		T15	8
valid_sources[0x0b]	12820	1			T1	68		T3	2		T15	16
valid_sources[0x0c]	12747	1			T2	9		T3	3		T15	15
valid_sources[0x0d]	12909	1			T3	2		T15	17		T16	4
valid_sources[0x0e]	14634	1			T2	6		T3	1		T15	13
valid_sources[0x0f]	15571	1			T2	17		T3	1		T15	11
valid_sources[0x10]	10983	1			T2	3		T3	4		T15	19
valid_sources[0x11]	16491	1			T2	8		T3	6		T15	21
valid_sources[0x12]	12138	1			T2	3		T3	3		T15	13
valid_sources[0x13]	14951	1			T2	9		T3	1		T15	19
valid_sources[0x14]	37930	1			T2	5		T3	2		T15	7
valid_sources[0x15]	16812	1			T2	3		T3	3		T14	2
valid_sources[0x16]	13908	1			T1	6		T2	7		T3	3
valid_sources[0x17]	11033	1			T3	5		T15	15		T16	7
valid_sources[0x18]	13462	1			T1	1219		T14	1		T15	12
valid_sources[0x19]	11659	1			T2	1		T3	5		T15	13
valid_sources[0x1a]	11504	1			T3	4		T15	10		T34	2
valid_sources[0x1b]	11352	1			T2	11		T3	1		T15	11
valid_sources[0x1c]	12886	1			T2	4		T3	3		T15	11
valid_sources[0x1d]	42419	1			T2	4		T3	2		T15	24
valid_sources[0x1e]	11086	1			T2	16		T3	2		T15	16
valid_sources[0x1f]	11461	1			T1	414		T2	13		T3	3
valid_sources[0x20]	12502	1			T2	2		T3	3		T15	18
valid_sources[0x21]	11228	1			T1	5		T2	3		T3	2
valid_sources[0x22]	12709	1			T2	13		T3	3		T15	12
valid_sources[0x23]	11388	1			T1	1		T2	3		T3	5
valid_sources[0x24]	14348	1			T1	1		T2	2		T3	4
valid_sources[0x25]	10993	1			T1	1		T2	1		T15	15
valid_sources[0x26]	12974	1			T3	1		T15	9		T16	11
valid_sources[0x27]	11588	1			T1	1		T2	1		T15	12
valid_sources[0x28]	14678	1			T2	7		T3	1		T15	17
valid_sources[0x29]	14386	1			T2	5		T3	1		T15	3
valid_sources[0x2a]	10924	1			T2	9		T3	4		T14	1
valid_sources[0x2b]	10982	1			T1	35		T3	5		T15	16
valid_sources[0x2c]	12603	1			T2	16		T3	1		T15	18
valid_sources[0x2d]	12518	1			T3	3		T15	12		T16	2
valid_sources[0x2e]	12823	1			T2	17		T3	3		T15	12
valid_sources[0x2f]	11230	1			T1	13		T2	4		T3	3
valid_sources[0x30]	11145	1			T2	1		T15	21		T16	2
valid_sources[0x31]	11259	1			T15	3		T16	13		T34	4
valid_sources[0x32]	19979	1			T2	6		T3	2		T15	8
valid_sources[0x33]	11572	1			T1	1		T2	13		T3	1
valid_sources[0x34]	28997	1			T2	9		T3	3		T15	13
valid_sources[0x35]	14575	1			T1	7		T2	22		T3	5
valid_sources[0x36]	14336	1			T1	1		T2	3		T3	4
valid_sources[0x37]	15420	1			T3	2		T15	14		T16	10
valid_sources[0x38]	13436	1			T2	4		T3	4		T15	7
valid_sources[0x39]	11427	1			T2	6		T3	1		T15	15
valid_sources[0x3a]	13280	1			T2	3		T3	2		T15	11
valid_sources[0x3b]	11918	1			T1	1		T2	6		T15	7
valid_sources[0x3c]	10966	1			T2	2		T3	2		T15	10
valid_sources[0x3d]	17324	1			T2	3		T15	10		T16	3
valid_sources[0x3e]	11594	1			T2	4		T3	1		T15	11
valid_sources[0x3f]	12225	1			T2	7		T15	15		T16	12
valid_sources[0x40]	11258	1			T2	9		T3	3		T15	14
valid_sources[0x41]	12610	1			T2	1		T3	7		T15	16
valid_sources[0x42]	12149	1			T3	6		T15	13		T16	1
valid_sources[0x43]	11108	1			T2	22		T3	4		T15	12
valid_sources[0x44]	11236	1			T1	2		T2	8		T3	1
valid_sources[0x45]	12947	1			T2	31		T3	3		T15	15
valid_sources[0x46]	13149	1			T2	3		T3	2		T15	16
valid_sources[0x47]	11403	1			T1	247		T2	12		T3	1
valid_sources[0x48]	12827	1			T2	22		T15	20		T16	10
valid_sources[0x49]	13797	1			T2	12		T3	3		T15	14
valid_sources[0x4a]	12718	1			T2	3		T15	15		T16	14
valid_sources[0x4b]	15357	1			T2	6		T3	6		T15	8
valid_sources[0x4c]	14014	1			T1	3		T3	1		T15	8
valid_sources[0x4d]	12239	1			T2	3		T3	1		T15	13
valid_sources[0x4e]	10780	1			T2	6		T3	2		T15	11
valid_sources[0x4f]	30502	1			T1	13		T2	5		T15	16
valid_sources[0x50]	11355	1			T1	29		T2	30		T15	12
valid_sources[0x51]	11304	1			T3	3		T15	9		T16	5
valid_sources[0x52]	12355	1			T2	6		T3	1		T15	12
valid_sources[0x53]	11402	1			T2	13		T15	9		T16	2
valid_sources[0x54]	19282	1			T2	10		T3	1		T15	17
valid_sources[0x55]	11676	1			T2	14		T3	1		T15	15
valid_sources[0x56]	13631	1			T2	12		T3	1		T15	13
valid_sources[0x57]	17850	1			T1	22		T2	3		T3	2
valid_sources[0x58]	21104	1			T2	5		T3	2		T15	12
valid_sources[0x59]	11249	1			T2	1		T3	1		T15	10
valid_sources[0x5a]	11564	1			T1	1		T2	13		T3	1
valid_sources[0x5b]	12047	1			T1	6		T2	4		T3	1
valid_sources[0x5c]	11328	1			T2	5		T3	1		T15	14
valid_sources[0x5d]	11894	1			T2	16		T3	2		T15	13
valid_sources[0x5e]	11257	1			T2	13		T3	5		T15	11
valid_sources[0x5f]	10855	1			T2	4		T3	3		T15	7
valid_sources[0x60]	12251	1			T1	1		T2	1		T15	13
valid_sources[0x61]	14887	1			T2	3		T3	2		T15	16
valid_sources[0x62]	12071	1			T2	6		T3	2		T15	16
valid_sources[0x63]	11625	1			T2	20		T15	16		T16	1
valid_sources[0x64]	55853	1			T2	10		T3	1		T14	1
valid_sources[0x65]	16224	1			T2	11		T15	11		T16	15
valid_sources[0x66]	11359	1			T1	391		T2	7		T3	1
valid_sources[0x67]	11371	1			T1	181		T2	1		T15	13
valid_sources[0x68]	12397	1			T1	199		T2	9		T15	19
valid_sources[0x69]	20766	1			T1	1		T2	21		T3	1
valid_sources[0x6a]	11867	1			T1	1		T2	8		T3	6
valid_sources[0x6b]	11930	1			T1	12		T2	9		T15	13
valid_sources[0x6c]	26537	1			T2	5		T3	2		T15	14
valid_sources[0x6d]	11453	1			T1	1		T2	8		T3	4
valid_sources[0x6e]	11679	1			T3	2		T15	12		T16	9
valid_sources[0x6f]	11094	1			T2	1		T3	3		T15	16
valid_sources[0x70]	15635	1			T2	23		T3	4		T15	22
valid_sources[0x71]	21221	1			T1	903		T2	7		T3	2
valid_sources[0x72]	11727	1			T2	13		T3	3		T15	12
valid_sources[0x73]	11006	1			T2	3		T3	1		T15	20
valid_sources[0x74]	16598	1			T1	2400		T2	8		T3	1
valid_sources[0x75]	15779	1			T1	1		T2	5		T15	15
valid_sources[0x76]	20091	1			T2	6		T15	14		T16	8
valid_sources[0x77]	11289	1			T1	1		T2	17		T3	3
valid_sources[0x78]	10916	1			T1	1		T2	13		T3	3
valid_sources[0x79]	11296	1			T2	4		T15	6		T16	7
valid_sources[0x7a]	11228	1			T2	6		T15	15		T16	3
valid_sources[0x7b]	11269	1			T1	14		T2	8		T3	3
valid_sources[0x7c]	18911	1			T2	4		T15	13		T26	7
valid_sources[0x7d]	11205	1			T2	17		T3	1		T15	14
valid_sources[0x7e]	12834	1			T2	18		T3	1		T15	11
valid_sources[0x7f]	13104	1			T1	1		T2	7		T3	1
valid_sources[0x80]	11987	1			T2	11		T3	1		T15	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

345948

1

T1

231

T2

243

T3

102

values[0x0]

all_enables

biggest_size

155801

1

T1

198

T2

107

T3

87

values[0x1]

all_enables

biggest_size

140122

1

T1

159

T2

79

T3

82