Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22125504	22314	0	0
attest_sw_binding_0_rd_A	22125504	2888	0	0
attest_sw_binding_1_rd_A	22125504	2783	0	0
attest_sw_binding_2_rd_A	22125504	2702	0	0
attest_sw_binding_3_rd_A	22125504	2604	0	0
attest_sw_binding_4_rd_A	22125504	2627	0	0
attest_sw_binding_5_rd_A	22125504	2632	0	0
attest_sw_binding_6_rd_A	22125504	2755	0	0
attest_sw_binding_7_rd_A	22125504	2813	0	0
intr_enable_rd_A	22125504	3407	0	0
key_version_rd_A	22125504	2790	0	0
max_creator_key_ver_regwen_rd_A	22125504	2740	0	0
max_owner_int_key_ver_regwen_rd_A	22125504	2715	0	0
max_owner_key_ver_regwen_rd_A	22125504	2738	0	0
reseed_interval_regwen_rd_A	22125504	2718	0	0
salt_0_rd_A	22125504	2636	0	0
salt_1_rd_A	22125504	2698	0	0
salt_2_rd_A	22125504	2849	0	0
salt_3_rd_A	22125504	2719	0	0
salt_4_rd_A	22125504	2616	0	0
salt_5_rd_A	22125504	2612	0	0
salt_6_rd_A	22125504	2872	0	0
salt_7_rd_A	22125504	2689	0	0
sealing_sw_binding_0_rd_A	22125504	2661	0	0
sealing_sw_binding_1_rd_A	22125504	2747	0	0
sealing_sw_binding_2_rd_A	22125504	2758	0	0
sealing_sw_binding_3_rd_A	22125504	2716	0	0
sealing_sw_binding_4_rd_A	22125504	2802	0	0
sealing_sw_binding_5_rd_A	22125504	2745	0	0
sealing_sw_binding_6_rd_A	22125504	2679	0	0
sealing_sw_binding_7_rd_A	22125504	2693	0	0
sideload_clear_rd_A	22125504	2603	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	22314	0	0
T9	12083	0	0	0
T15	13308	263	0	0
T16	18990	0	0	0
T17	967	0	0	0
T18	801	0	0	0
T26	10799	0	0	0
T27	19088	676	0	0
T34	4989	0	0	0
T35	7301	0	0	0
T46	0	35	0	0
T47	0	1033	0	0
T77	0	566	0	0
T115	0	57	0	0
T134	0	232	0	0
T135	0	528	0	0
T136	0	56	0	0
T137	1054	0	0	0
T138	0	885	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2888	0	0
T42	5925	0	0	0
T46	0	37	0	0
T56	133662	0	0	0
T115	18439	46	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	40	0	0
T175	0	15	0	0
T176	0	36	0	0
T177	0	20	0	0
T178	0	4	0	0
T179	0	65	0	0
T180	0	8	0	0
T181	0	3	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2783	0	0
T42	5925	0	0	0
T46	0	37	0	0
T56	133662	0	0	0
T115	18439	29	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	23	0	0
T175	0	24	0	0
T176	0	17	0	0
T177	0	24	0	0
T179	0	68	0	0
T180	0	9	0	0
T181	0	12	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T187	0	1	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2702	0	0
T42	5925	0	0	0
T46	0	9	0	0
T56	133662	0	0	0
T115	18439	12	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	37	0	0
T175	0	28	0	0
T176	0	31	0	0
T177	0	9	0	0
T179	0	39	0	0
T180	0	11	0	0
T181	0	8	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T188	0	10	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2604	0	0
T42	5925	0	0	0
T46	0	20	0	0
T56	133662	0	0	0
T115	18439	43	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	29	0	0
T175	0	22	0	0
T176	0	17	0	0
T177	0	4	0	0
T179	0	44	0	0
T180	0	4	0	0
T181	0	5	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	8	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2627	0	0
T42	5925	0	0	0
T46	0	38	0	0
T56	133662	0	0	0
T115	18439	21	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	28	0	0
T175	0	8	0	0
T176	0	22	0	0
T177	0	28	0	0
T179	0	60	0	0
T180	0	18	0	0
T181	0	2	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	4	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2632	0	0
T42	5925	0	0	0
T46	0	37	0	0
T56	133662	0	0	0
T115	18439	34	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	25	0	0
T175	0	15	0	0
T176	0	63	0	0
T177	0	13	0	0
T179	0	63	0	0
T180	0	15	0	0
T181	0	8	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	6	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2755	0	0
T42	5925	0	0	0
T46	0	11	0	0
T56	133662	0	0	0
T115	18439	14	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	28	0	0
T175	0	19	0	0
T176	0	31	0	0
T177	0	18	0	0
T179	0	48	0	0
T180	0	18	0	0
T181	0	8	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	7	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2813	0	0
T42	5925	0	0	0
T46	0	16	0	0
T56	133662	0	0	0
T115	18439	36	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	27	0	0
T175	0	22	0	0
T176	0	37	0	0
T177	0	19	0	0
T179	0	52	0	0
T180	0	7	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	6	0	0
T190	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	3407	0	0
T42	5925	0	0	0
T46	0	29	0	0
T56	133662	25	0	0
T80	0	21	0	0
T84	0	37	0	0
T87	0	28	0	0
T89	0	64	0	0
T115	18439	83	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	22	0	0
T175	0	22	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T191	0	94	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2790	0	0
T42	5925	0	0	0
T46	0	17	0	0
T56	133662	0	0	0
T115	18439	30	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	37	0	0
T175	0	8	0	0
T176	0	32	0	0
T177	0	14	0	0
T179	0	48	0	0
T181	0	3	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T188	0	19	0	0
T189	0	2	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2740	0	0
T42	5925	0	0	0
T46	0	51	0	0
T56	133662	0	0	0
T115	18439	28	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	26	0	0
T175	0	8	0	0
T176	0	51	0	0
T177	0	19	0	0
T179	0	57	0	0
T180	0	10	0	0
T181	0	23	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T192	0	7	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2715	0	0
T42	5925	0	0	0
T46	0	44	0	0
T56	133662	0	0	0
T115	18439	25	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	29	0	0
T175	0	11	0	0
T176	0	42	0	0
T177	0	8	0	0
T179	0	43	0	0
T180	0	11	0	0
T181	0	10	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	8	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2738	0	0
T42	5925	0	0	0
T46	0	27	0	0
T56	133662	0	0	0
T115	18439	16	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	51	0	0
T175	0	17	0	0
T176	0	63	0	0
T177	0	7	0	0
T179	0	35	0	0
T180	0	23	0	0
T181	0	3	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	3	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2718	0	0
T42	5925	0	0	0
T46	0	24	0	0
T56	133662	0	0	0
T115	18439	27	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	17	0	0
T175	0	7	0	0
T176	0	40	0	0
T177	0	10	0	0
T179	0	51	0	0
T180	0	1	0	0
T181	0	6	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	9	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2636	0	0
T42	5925	0	0	0
T46	0	35	0	0
T56	133662	0	0	0
T115	18439	24	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T126	0	94	0	0
T134	0	19	0	0
T176	0	35	0	0
T177	0	18	0	0
T179	0	22	0	0
T181	0	6	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T188	0	19	0	0
T189	0	4	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2698	0	0
T42	5925	0	0	0
T46	0	25	0	0
T56	133662	0	0	0
T115	18439	22	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	37	0	0
T175	0	36	0	0
T176	0	51	0	0
T177	0	11	0	0
T179	0	71	0	0
T180	0	8	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T188	0	29	0	0
T189	0	4	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2849	0	0
T42	5925	0	0	0
T46	0	39	0	0
T56	133662	0	0	0
T115	18439	39	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	47	0	0
T175	0	7	0	0
T176	0	46	0	0
T177	0	11	0	0
T179	0	44	0	0
T180	0	16	0	0
T181	0	14	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	4	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2719	0	0
T42	5925	0	0	0
T46	0	24	0	0
T56	133662	0	0	0
T115	18439	57	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	43	0	0
T175	0	13	0	0
T176	0	54	0	0
T177	0	35	0	0
T179	0	67	0	0
T180	0	8	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T188	0	22	0	0
T189	0	3	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2616	0	0
T42	5925	0	0	0
T46	0	24	0	0
T56	133662	0	0	0
T115	18439	35	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	9	0	0
T175	0	17	0	0
T176	0	22	0	0
T177	0	25	0	0
T179	0	58	0	0
T180	0	1	0	0
T181	0	2	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	3	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2612	0	0
T42	5925	0	0	0
T46	0	31	0	0
T56	133662	0	0	0
T115	18439	28	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T126	0	58	0	0
T134	0	23	0	0
T176	0	36	0	0
T177	0	12	0	0
T179	0	59	0	0
T180	0	18	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T188	0	17	0	0
T189	0	7	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2872	0	0
T42	5925	0	0	0
T46	0	36	0	0
T56	133662	0	0	0
T115	18439	25	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	27	0	0
T175	0	10	0	0
T176	0	47	0	0
T177	0	12	0	0
T179	0	57	0	0
T180	0	7	0	0
T181	0	5	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T188	0	17	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2689	0	0
T42	5925	0	0	0
T46	0	30	0	0
T56	133662	0	0	0
T69	0	1	0	0
T115	18439	27	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	26	0	0
T175	0	27	0	0
T176	0	28	0	0
T177	0	14	0	0
T179	0	72	0	0
T180	0	2	0	0
T181	0	2	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2661	0	0
T42	5925	0	0	0
T46	0	24	0	0
T56	133662	0	0	0
T115	18439	23	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	34	0	0
T175	0	24	0	0
T176	0	28	0	0
T177	0	20	0	0
T179	0	55	0	0
T180	0	5	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T188	0	22	0	0
T189	0	8	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2747	0	0
T42	5925	0	0	0
T46	0	27	0	0
T56	133662	0	0	0
T115	18439	11	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	29	0	0
T175	0	21	0	0
T176	0	33	0	0
T177	0	20	0	0
T179	0	54	0	0
T180	0	13	0	0
T181	0	17	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	5	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2758	0	0
T42	5925	0	0	0
T46	0	21	0	0
T56	133662	0	0	0
T115	18439	17	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	21	0	0
T175	0	31	0	0
T176	0	43	0	0
T177	0	24	0	0
T179	0	61	0	0
T180	0	35	0	0
T181	0	5	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	2	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2716	0	0
T42	5925	0	0	0
T46	0	24	0	0
T56	133662	0	0	0
T115	18439	24	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	16	0	0
T175	0	17	0	0
T176	0	35	0	0
T177	0	4	0	0
T179	0	47	0	0
T180	0	4	0	0
T181	0	9	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	4	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2802	0	0
T42	5925	0	0	0
T46	0	31	0	0
T56	133662	0	0	0
T115	18439	59	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	28	0	0
T175	0	6	0	0
T176	0	40	0	0
T179	0	58	0	0
T180	0	12	0	0
T181	0	6	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T188	0	14	0	0
T189	0	6	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2745	0	0
T42	5925	0	0	0
T46	0	15	0	0
T56	133662	0	0	0
T115	18439	32	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	10	0	0
T175	0	11	0	0
T176	0	30	0	0
T177	0	27	0	0
T179	0	61	0	0
T180	0	20	0	0
T181	0	3	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	9	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2679	0	0
T42	5925	0	0	0
T46	0	20	0	0
T56	133662	0	0	0
T115	18439	34	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	34	0	0
T175	0	28	0	0
T176	0	39	0	0
T177	0	4	0	0
T179	0	66	0	0
T180	0	6	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T188	0	14	0	0
T189	0	5	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2693	0	0
T42	5925	0	0	0
T46	0	10	0	0
T56	133662	0	0	0
T115	18439	21	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	47	0	0
T175	0	2	0	0
T176	0	52	0	0
T177	0	12	0	0
T179	0	62	0	0
T180	0	16	0	0
T181	0	16	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	3	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125504	2603	0	0
T42	5925	0	0	0
T46	0	31	0	0
T56	133662	0	0	0
T115	18439	37	0	0
T116	11943	0	0	0
T117	9463	0	0	0
T134	0	43	0	0
T175	0	11	0	0
T176	0	47	0	0
T177	0	15	0	0
T179	0	34	0	0
T180	0	5	0	0
T181	0	3	0	0
T182	5867	0	0	0
T183	2029	0	0	0
T184	45523	0	0	0
T185	3728	0	0	0
T186	19627	0	0	0
T189	0	2	0	0