Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2362809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

600039

1

T1

147

T2

289

T3

193

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2553649	1			T1	482		T2	554		T3	384
values[0x0]	202792	1			T1	38		T2	119		T3	56
values[0x1]	206407	1			T1	51		T2	112		T3	64

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1631240	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1331608

1

T1

269

T2

437

T3

250

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13123	1			T1	3		T2	4		T4	5
valid_sources[0x01]	8718	1			T1	3		T2	7		T4	1
valid_sources[0x02]	12801	1			T1	2		T2	3		T4	35
valid_sources[0x03]	30974	1			T1	3		T2	1		T14	8
valid_sources[0x04]	9121	1			T2	1		T14	4		T16	36
valid_sources[0x05]	10648	1			T1	1		T2	2		T4	7
valid_sources[0x06]	9353	1			T1	2		T4	9		T14	3
valid_sources[0x07]	9960	1			T1	2		T2	2		T4	13
valid_sources[0x08]	9455	1			T1	4		T2	2		T14	1
valid_sources[0x09]	10177	1			T1	1		T2	4		T14	6
valid_sources[0x0a]	9967	1			T2	5		T13	8		T14	6
valid_sources[0x0b]	10520	1			T1	1		T2	3		T16	40
valid_sources[0x0c]	9469	1			T1	1		T2	1		T4	8
valid_sources[0x0d]	10389	1			T1	1		T4	14		T14	4
valid_sources[0x0e]	9340	1			T1	5		T2	2		T4	1
valid_sources[0x0f]	9395	1			T1	1		T2	5		T4	4
valid_sources[0x10]	9060	1			T1	6		T2	3		T14	5
valid_sources[0x11]	29482	1			T2	1		T4	15		T14	5
valid_sources[0x12]	11108	1			T2	6		T14	7		T15	463
valid_sources[0x13]	8257	1			T2	7		T4	20		T13	106
valid_sources[0x14]	15011	1			T1	4		T2	4		T4	5
valid_sources[0x15]	9359	1			T1	1		T2	2		T4	13
valid_sources[0x16]	9552	1			T1	1		T2	1		T14	3
valid_sources[0x17]	9213	1			T1	2		T4	4		T14	2
valid_sources[0x18]	8463	1			T1	5		T2	7		T4	17
valid_sources[0x19]	8545	1			T1	4		T2	1		T13	65
valid_sources[0x1a]	11341	1			T2	3		T14	5		T16	39
valid_sources[0x1b]	10409	1			T1	2		T2	1		T4	23
valid_sources[0x1c]	8749	1			T1	1		T2	3		T14	4
valid_sources[0x1d]	9443	1			T1	3		T2	7		T4	4
valid_sources[0x1e]	9059	1			T1	3		T2	6		T14	3
valid_sources[0x1f]	13427	1			T1	3		T2	1		T4	5
valid_sources[0x20]	9960	1			T1	2		T4	5		T14	2
valid_sources[0x21]	8771	1			T1	2		T4	10		T14	4
valid_sources[0x22]	8395	1			T1	2		T2	9		T4	3
valid_sources[0x23]	9317	1			T1	4		T2	4		T4	16
valid_sources[0x24]	16362	1			T1	1		T2	7		T4	6
valid_sources[0x25]	9101	1			T1	2		T2	1		T14	4
valid_sources[0x26]	8936	1			T1	6		T2	2		T4	9
valid_sources[0x27]	8516	1			T1	3		T2	4		T14	9
valid_sources[0x28]	8760	1			T1	2		T2	7		T14	9
valid_sources[0x29]	8531	1			T1	1		T2	1		T4	9
valid_sources[0x2a]	8797	1			T1	1		T2	1		T3	504
valid_sources[0x2b]	9302	1			T2	5		T4	16		T14	11
valid_sources[0x2c]	9610	1			T1	3		T2	7		T4	1
valid_sources[0x2d]	8542	1			T1	5		T2	6		T4	1
valid_sources[0x2e]	11325	1			T1	5		T2	1		T14	6
valid_sources[0x2f]	9451	1			T1	2		T2	2		T4	7
valid_sources[0x30]	8376	1			T1	5		T2	11		T4	7
valid_sources[0x31]	8964	1			T1	1		T2	9		T4	1
valid_sources[0x32]	9135	1			T1	7		T2	9		T4	3
valid_sources[0x33]	9007	1			T1	2		T2	3		T4	2
valid_sources[0x34]	8566	1			T2	2		T4	9		T13	18
valid_sources[0x35]	9328	1			T1	3		T2	2		T4	7
valid_sources[0x36]	15898	1			T2	5		T4	3		T14	1
valid_sources[0x37]	11809	1			T1	2		T2	2		T4	2
valid_sources[0x38]	8636	1			T2	1		T13	4		T14	1
valid_sources[0x39]	13574	1			T1	2		T4	18		T14	3
valid_sources[0x3a]	10740	1			T1	3		T2	2		T4	1
valid_sources[0x3b]	13931	1			T4	3		T14	1		T16	50
valid_sources[0x3c]	9529	1			T1	5		T2	5		T14	11
valid_sources[0x3d]	9050	1			T1	1		T2	1		T4	5
valid_sources[0x3e]	10665	1			T2	3		T14	7		T16	60
valid_sources[0x3f]	10038	1			T1	4		T2	7		T14	4
valid_sources[0x40]	8200	1			T2	2		T14	4		T16	50
valid_sources[0x41]	8274	1			T1	2		T14	3		T16	56
valid_sources[0x42]	10260	1			T1	2		T2	4		T4	1
valid_sources[0x43]	23817	1			T1	2		T2	3		T4	4
valid_sources[0x44]	15106	1			T1	4		T4	41		T14	7
valid_sources[0x45]	11021	1			T1	3		T2	3		T13	86
valid_sources[0x46]	9305	1			T1	2		T2	4		T4	4
valid_sources[0x47]	10666	1			T1	2		T2	5		T14	4
valid_sources[0x48]	8844	1			T2	9		T14	5		T16	36
valid_sources[0x49]	10355	1			T1	1		T2	2		T4	12
valid_sources[0x4a]	10028	1			T1	3		T2	4		T4	8
valid_sources[0x4b]	9510	1			T1	5		T2	3		T14	8
valid_sources[0x4c]	9711	1			T1	4		T2	1		T4	11
valid_sources[0x4d]	11003	1			T1	4		T2	6		T4	2
valid_sources[0x4e]	9319	1			T1	1		T2	3		T14	5
valid_sources[0x4f]	14326	1			T1	4		T2	1		T4	20
valid_sources[0x50]	9119	1			T2	1		T4	13		T14	3
valid_sources[0x51]	8368	1			T1	1		T2	4		T4	1
valid_sources[0x52]	23228	1			T1	5		T2	3		T4	3
valid_sources[0x53]	9190	1			T1	3		T4	10		T14	2
valid_sources[0x54]	29053	1			T1	1		T2	2		T13	142
valid_sources[0x55]	8927	1			T2	3		T4	2		T14	3
valid_sources[0x56]	8029	1			T1	4		T2	3		T4	7
valid_sources[0x57]	11812	1			T4	27		T14	3		T16	56
valid_sources[0x58]	9711	1			T1	1		T2	3		T4	7
valid_sources[0x59]	12341	1			T1	1		T2	3		T14	4
valid_sources[0x5a]	9083	1			T1	3		T2	6		T14	11
valid_sources[0x5b]	8721	1			T1	2		T2	3		T14	6
valid_sources[0x5c]	9253	1			T2	2		T14	3		T16	37
valid_sources[0x5d]	8702	1			T4	11		T14	3		T16	43
valid_sources[0x5e]	11425	1			T2	2		T4	2		T16	38
valid_sources[0x5f]	8784	1			T1	4		T2	3		T14	4
valid_sources[0x60]	8816	1			T1	2		T2	1		T4	10
valid_sources[0x61]	27113	1			T1	2		T2	3		T14	5
valid_sources[0x62]	8262	1			T1	5		T2	1		T14	7
valid_sources[0x63]	10310	1			T1	3		T2	8		T14	7
valid_sources[0x64]	8938	1			T1	4		T2	2		T14	9
valid_sources[0x65]	8667	1			T1	4		T2	1		T4	7
valid_sources[0x66]	18305	1			T2	1		T14	6		T16	31
valid_sources[0x67]	8269	1			T1	4		T4	1		T14	11
valid_sources[0x68]	15384	1			T1	2		T2	6		T4	10
valid_sources[0x69]	11830	1			T1	1		T4	17		T14	4
valid_sources[0x6a]	11632	1			T1	7		T2	3		T4	7
valid_sources[0x6b]	9464	1			T1	4		T2	8		T4	6
valid_sources[0x6c]	8528	1			T2	5		T4	13		T14	2
valid_sources[0x6d]	10778	1			T1	7		T2	4		T4	6
valid_sources[0x6e]	10187	1			T1	2		T2	6		T4	4
valid_sources[0x6f]	13788	1			T1	1		T2	5		T4	11
valid_sources[0x70]	11382	1			T1	7		T2	5		T4	4
valid_sources[0x71]	11501	1			T1	1		T2	3		T14	7
valid_sources[0x72]	25384	1			T2	2		T4	14		T14	9
valid_sources[0x73]	11129	1			T1	2		T2	2		T13	1
valid_sources[0x74]	13426	1			T1	2		T14	7		T16	47
valid_sources[0x75]	12937	1			T1	1		T2	2		T4	3
valid_sources[0x76]	28115	1			T1	1		T4	6		T14	8
valid_sources[0x77]	10146	1			T1	5		T2	2		T4	4
valid_sources[0x78]	8816	1			T1	1		T2	5		T4	4
valid_sources[0x79]	8845	1			T1	1		T2	6		T14	5
valid_sources[0x7a]	15441	1			T1	1		T2	1		T4	17
valid_sources[0x7b]	13536	1			T1	1		T2	2		T4	9
valid_sources[0x7c]	10035	1			T1	2		T2	1		T14	6
valid_sources[0x7d]	10053	1			T4	17		T14	6		T16	45
valid_sources[0x7e]	9591	1			T1	5		T4	1		T5	782
valid_sources[0x7f]	8693	1			T1	4		T2	2		T13	161
valid_sources[0x80]	15763	1			T1	1		T4	4		T14	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

321222

1

T1

124

T2

165

T3

139

values[0x0]

all_enables

biggest_size

146341

1

T1

12

T2

76

T3

30

values[0x1]

all_enables

biggest_size

132476

1

T1

11

T2

48

T3

24