SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[keymgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 3008834 | 0 | T1 | 571 | T2 | 785 | T3 | 504 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3008613 | 1 | T1 | 571 | T2 | 785 | T3 | 504 | ||||
values[1] | 22 | 1 | T33 | 1 | T377 | 1 | T378 | 1 | ||||
values[2] | 3 | 1 | T379 | 1 | T186 | 1 | T380 | 1 | ||||
values[3] | 115 | 1 | T118 | 1 | T57 | 1 | T39 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3008612 | 1 | T1 | 571 | T2 | 785 | T3 | 504 | ||||
values[1] | 27 | 1 | T192 | 1 | T377 | 1 | T381 | 1 | ||||
values[2] | 7 | 1 | T180 | 1 | T178 | 1 | T181 | 1 | ||||
values[3] | 99 | 1 | T33 | 1 | T35 | 1 | T57 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3008504 | 1 | T1 | 571 | T2 | 785 | T3 | 504 | ||||
auto[TlIntgErrCmd] | 108 | 1 | T32 | 1 | T382 | 1 | T383 | 1 | ||||
auto[TlIntgErrData] | 109 | 1 | T35 | 1 | T384 | 1 | T192 | 1 | ||||
auto[TlIntgErrBoth] | 113 | 1 | T33 | 1 | T118 | 1 | T57 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |