Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3355342	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

649574

1

T1

4188

T2

283

T3

379

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3569822	1			T1	5994		T2	546		T3	426
values[0x0]	216091	1			T1	1527		T2	72		T3	135
values[0x1]	219003	1			T1	1479		T2	62		T3	133

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2299178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1705738

1

T1

5404

T2

360

T3

444

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13144	1			T12	13		T13	17		T14	9
valid_sources[0x01]	13453	1			T12	7		T13	11		T14	5
valid_sources[0x02]	25361	1			T2	6		T4	1		T13	8
valid_sources[0x03]	12575	1			T2	1		T12	2		T4	33
valid_sources[0x04]	12809	1			T2	6		T12	13		T13	18
valid_sources[0x05]	13930	1			T2	5		T13	13		T14	1
valid_sources[0x06]	12319	1			T12	7		T4	30		T13	2
valid_sources[0x07]	12421	1			T2	2		T12	20		T13	18
valid_sources[0x08]	13342	1			T12	3		T13	7		T15	1
valid_sources[0x09]	13272	1			T2	1		T12	5		T13	12
valid_sources[0x0a]	13227	1			T12	4		T13	14		T14	31
valid_sources[0x0b]	33390	1			T2	2		T12	9		T13	1
valid_sources[0x0c]	12641	1			T12	3		T13	5		T16	7
valid_sources[0x0d]	11956	1			T2	2		T12	1		T13	8
valid_sources[0x0e]	13872	1			T1	13		T12	8		T13	3
valid_sources[0x0f]	13611	1			T2	1		T12	4		T13	12
valid_sources[0x10]	14682	1			T2	2		T4	3		T13	8
valid_sources[0x11]	12791	1			T2	1		T12	4		T13	1
valid_sources[0x12]	15072	1			T2	7		T12	6		T13	6
valid_sources[0x13]	13438	1			T12	7		T13	5		T16	5
valid_sources[0x14]	14652	1			T2	1		T12	1		T13	6
valid_sources[0x15]	13454	1			T2	3		T12	3		T4	44
valid_sources[0x16]	19830	1			T2	1		T12	12		T13	13
valid_sources[0x17]	17664	1			T3	1		T12	24		T13	5
valid_sources[0x18]	14101	1			T12	4		T13	6		T15	1
valid_sources[0x19]	17265	1			T3	1		T12	9		T13	5
valid_sources[0x1a]	13089	1			T2	3		T12	30		T13	4
valid_sources[0x1b]	13390	1			T13	2		T14	49		T15	1
valid_sources[0x1c]	16188	1			T13	9		T14	346		T15	6
valid_sources[0x1d]	16836	1			T2	6		T3	308		T12	3
valid_sources[0x1e]	17044	1			T12	2		T13	7		T15	1
valid_sources[0x1f]	12822	1			T12	1		T13	14		T14	4
valid_sources[0x20]	14104	1			T12	5		T13	5		T16	8
valid_sources[0x21]	12703	1			T12	3		T13	4		T14	3
valid_sources[0x22]	13517	1			T2	14		T12	6		T4	35
valid_sources[0x23]	18437	1			T2	1		T13	8		T15	1
valid_sources[0x24]	105381	1			T2	2		T12	2		T13	7
valid_sources[0x25]	14777	1			T2	7		T3	1		T12	9
valid_sources[0x26]	14018	1			T2	1		T12	39		T13	13
valid_sources[0x27]	13492	1			T12	5		T13	3		T15	2
valid_sources[0x28]	13089	1			T4	76		T13	14		T15	1
valid_sources[0x29]	13813	1			T2	2		T12	16		T13	6
valid_sources[0x2a]	14098	1			T12	20		T4	68		T13	2
valid_sources[0x2b]	14368	1			T2	15		T12	15		T13	1
valid_sources[0x2c]	13198	1			T2	3		T12	14		T13	11
valid_sources[0x2d]	75891	1			T1	18		T12	24		T4	2
valid_sources[0x2e]	12707	1			T4	6		T13	7		T15	2
valid_sources[0x2f]	12252	1			T2	2		T12	22		T13	11
valid_sources[0x30]	13808	1			T2	18		T12	24		T13	4
valid_sources[0x31]	13624	1			T12	23		T13	4		T14	3
valid_sources[0x32]	14967	1			T2	5		T13	8		T14	13
valid_sources[0x33]	13811	1			T2	3		T13	4		T14	1
valid_sources[0x34]	14101	1			T3	1		T12	1		T13	14
valid_sources[0x35]	14396	1			T2	7		T4	29		T13	7
valid_sources[0x36]	12728	1			T12	6		T13	3		T15	2
valid_sources[0x37]	13885	1			T13	12		T14	5		T16	9
valid_sources[0x38]	12491	1			T12	20		T4	32		T13	8
valid_sources[0x39]	12829	1			T12	21		T13	13		T14	4
valid_sources[0x3a]	15224	1			T2	3		T12	7		T13	3
valid_sources[0x3b]	13363	1			T12	4		T13	9		T16	9
valid_sources[0x3c]	12503	1			T12	15		T13	4		T16	6
valid_sources[0x3d]	12336	1			T2	12		T13	7		T15	1
valid_sources[0x3e]	20000	1			T1	12		T12	14		T13	4
valid_sources[0x3f]	12798	1			T2	3		T12	3		T4	13
valid_sources[0x40]	21865	1			T2	3		T12	17		T13	14
valid_sources[0x41]	13314	1			T12	13		T13	10		T15	1
valid_sources[0x42]	12301	1			T2	1		T12	13		T13	8
valid_sources[0x43]	13290	1			T2	3		T3	1		T12	11
valid_sources[0x44]	14249	1			T13	7		T14	73		T16	5
valid_sources[0x45]	17972	1			T2	2		T13	17		T15	1
valid_sources[0x46]	13000	1			T2	5		T12	2		T13	9
valid_sources[0x47]	19366	1			T2	7		T12	6		T13	7
valid_sources[0x48]	16746	1			T2	1		T12	8		T4	2
valid_sources[0x49]	14770	1			T2	6		T12	18		T13	5
valid_sources[0x4a]	13001	1			T14	86		T15	4		T16	5
valid_sources[0x4b]	15042	1			T2	20		T12	35		T13	11
valid_sources[0x4c]	12291	1			T2	1		T12	2		T13	3
valid_sources[0x4d]	14346	1			T12	2		T13	6		T14	8
valid_sources[0x4e]	20340	1			T3	1		T12	6		T13	10
valid_sources[0x4f]	12400	1			T2	12		T12	15		T13	10
valid_sources[0x50]	17101	1			T12	2		T13	18		T14	7
valid_sources[0x51]	12205	1			T13	14		T14	3		T15	4
valid_sources[0x52]	12841	1			T12	8		T13	6		T15	1
valid_sources[0x53]	14428	1			T12	11		T13	11		T15	1
valid_sources[0x54]	15047	1			T2	4		T12	1		T13	8
valid_sources[0x55]	12411	1			T2	10		T3	1		T14	56
valid_sources[0x56]	12861	1			T13	3		T14	4		T15	2
valid_sources[0x57]	13102	1			T13	7		T15	1		T16	7
valid_sources[0x58]	13364	1			T12	19		T13	4		T15	1
valid_sources[0x59]	13841	1			T15	2		T16	6		T17	13
valid_sources[0x5a]	13597	1			T2	7		T13	11		T15	4
valid_sources[0x5b]	15028	1			T2	17		T12	1		T13	1
valid_sources[0x5c]	13292	1			T2	9		T12	4		T4	1
valid_sources[0x5d]	12376	1			T2	11		T12	2		T13	5
valid_sources[0x5e]	14837	1			T2	4		T12	17		T13	14
valid_sources[0x5f]	12490	1			T2	1		T12	1		T13	7
valid_sources[0x60]	12611	1			T2	13		T12	10		T13	15
valid_sources[0x61]	13551	1			T12	13		T4	4		T13	11
valid_sources[0x62]	13772	1			T2	4		T12	4		T13	5
valid_sources[0x63]	15408	1			T12	22		T13	14		T14	250
valid_sources[0x64]	18623	1			T12	13		T13	9		T16	5
valid_sources[0x65]	12562	1			T2	5		T13	6		T16	5
valid_sources[0x66]	13404	1			T2	11		T13	6		T14	3
valid_sources[0x67]	15132	1			T2	15		T13	2		T14	11
valid_sources[0x68]	11884	1			T12	1		T13	6		T14	1
valid_sources[0x69]	13409	1			T2	1		T3	1		T12	10
valid_sources[0x6a]	12117	1			T12	3		T13	11		T16	3
valid_sources[0x6b]	14563	1			T12	4		T4	6		T13	3
valid_sources[0x6c]	13013	1			T12	11		T4	16		T13	7
valid_sources[0x6d]	15081	1			T2	2		T12	4		T13	5
valid_sources[0x6e]	18691	1			T3	1		T12	9		T13	17
valid_sources[0x6f]	14287	1			T12	19		T13	6		T15	6
valid_sources[0x70]	13762	1			T12	3		T13	3		T14	4
valid_sources[0x71]	24797	1			T2	9		T12	1		T13	6
valid_sources[0x72]	12043	1			T12	3		T13	1		T14	77
valid_sources[0x73]	14827	1			T2	1		T12	23		T13	14
valid_sources[0x74]	13738	1			T2	1		T13	9		T15	2
valid_sources[0x75]	12114	1			T2	2		T12	12		T13	2
valid_sources[0x76]	13544	1			T2	1		T12	3		T13	28
valid_sources[0x77]	12492	1			T3	97		T12	5		T15	1
valid_sources[0x78]	13732	1			T12	6		T4	114		T13	2
valid_sources[0x79]	12603	1			T2	1		T12	15		T13	11
valid_sources[0x7a]	12281	1			T12	8		T13	8		T15	2
valid_sources[0x7b]	14725	1			T12	7		T13	8		T14	87
valid_sources[0x7c]	13750	1			T2	5		T12	1		T15	1
valid_sources[0x7d]	60887	1			T2	7		T13	10		T14	9
valid_sources[0x7e]	11882	1			T2	3		T12	3		T13	1
valid_sources[0x7f]	12320	1			T2	9		T12	13		T13	5
valid_sources[0x80]	14876	1			T2	1		T12	12		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

354223

1

T1

2139

T2

233

T3

184

values[0x0]

all_enables

biggest_size

155269

1

T1

1090

T2

31

T3

97

values[0x1]

all_enables

biggest_size

140082

1

T1

959

T2

19

T3

98