Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26581190	16219	0	0
attest_sw_binding_0_rd_A	26581190	1937	0	0
attest_sw_binding_1_rd_A	26581190	1916	0	0
attest_sw_binding_2_rd_A	26581190	1954	0	0
attest_sw_binding_3_rd_A	26581190	1960	0	0
attest_sw_binding_4_rd_A	26581190	1835	0	0
attest_sw_binding_5_rd_A	26581190	1831	0	0
attest_sw_binding_6_rd_A	26581190	2084	0	0
attest_sw_binding_7_rd_A	26581190	2018	0	0
intr_enable_rd_A	26581190	2596	0	0
key_version_rd_A	26581190	1988	0	0
max_creator_key_ver_regwen_rd_A	26581190	2007	0	0
max_owner_int_key_ver_regwen_rd_A	26581190	1847	0	0
max_owner_key_ver_regwen_rd_A	26581190	1916	0	0
reseed_interval_regwen_rd_A	26581190	1917	0	0
salt_0_rd_A	26581190	2028	0	0
salt_1_rd_A	26581190	1895	0	0
salt_2_rd_A	26581190	1927	0	0
salt_3_rd_A	26581190	1935	0	0
salt_4_rd_A	26581190	1972	0	0
salt_5_rd_A	26581190	1833	0	0
salt_6_rd_A	26581190	1905	0	0
salt_7_rd_A	26581190	1863	0	0
sealing_sw_binding_0_rd_A	26581190	2023	0	0
sealing_sw_binding_1_rd_A	26581190	1967	0	0
sealing_sw_binding_2_rd_A	26581190	1887	0	0
sealing_sw_binding_3_rd_A	26581190	1990	0	0
sealing_sw_binding_4_rd_A	26581190	1974	0	0
sealing_sw_binding_5_rd_A	26581190	2052	0	0
sealing_sw_binding_6_rd_A	26581190	1963	0	0
sealing_sw_binding_7_rd_A	26581190	1939	0	0
sideload_clear_rd_A	26581190	1926	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	16219	0	0
T40	9650	0	0	0
T48	19076	290	0	0
T51	0	110	0	0
T53	0	86	0	0
T57	3022	0	0	0
T69	0	416	0	0
T71	0	755	0	0
T82	7373	0	0	0
T95	30596	165	0	0
T100	0	127	0	0
T118	0	416	0	0
T119	0	72	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T127	0	1	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1937	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	25	0	0
T53	0	40	0	0
T57	3022	0	0	0
T75	0	23	0	0
T82	7373	0	0	0
T95	30596	34	0	0
T100	0	83	0	0
T119	0	18	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	33	0	0
T181	0	19	0	0
T182	0	20	0	0
T183	0	56	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1916	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	5	0	0
T53	0	27	0	0
T57	3022	0	0	0
T75	0	57	0	0
T82	7373	0	0	0
T95	30596	21	0	0
T100	0	60	0	0
T119	0	32	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	15	0	0
T181	0	4	0	0
T182	0	48	0	0
T183	0	49	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1954	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	28	0	0
T53	0	23	0	0
T57	3022	0	0	0
T75	0	73	0	0
T82	7373	0	0	0
T95	30596	35	0	0
T100	0	75	0	0
T119	0	12	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	48	0	0
T181	0	21	0	0
T182	0	58	0	0
T183	0	36	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1960	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	24	0	0
T53	0	40	0	0
T57	3022	0	0	0
T75	0	73	0	0
T82	7373	0	0	0
T95	30596	27	0	0
T100	0	81	0	0
T119	0	29	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	35	0	0
T181	0	22	0	0
T182	0	35	0	0
T183	0	57	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1835	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	14	0	0
T53	0	15	0	0
T57	3022	0	0	0
T75	0	34	0	0
T82	7373	0	0	0
T95	30596	21	0	0
T100	0	93	0	0
T119	0	28	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	23	0	0
T182	0	39	0	0
T183	0	85	0	0
T184	0	2	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1831	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	20	0	0
T53	0	20	0	0
T57	3022	0	0	0
T75	0	56	0	0
T82	7373	0	0	0
T95	30596	36	0	0
T100	0	54	0	0
T119	0	43	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	20	0	0
T181	0	10	0	0
T182	0	26	0	0
T183	0	68	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	2084	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	32	0	0
T53	0	20	0	0
T57	3022	0	0	0
T75	0	81	0	0
T82	7373	0	0	0
T95	30596	28	0	0
T100	0	110	0	0
T119	0	32	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	38	0	0
T181	0	12	0	0
T182	0	41	0	0
T183	0	61	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	2018	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	34	0	0
T53	0	38	0	0
T57	3022	0	0	0
T75	0	60	0	0
T82	7373	0	0	0
T95	30596	44	0	0
T100	0	85	0	0
T119	0	29	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	22	0	0
T181	0	10	0	0
T182	0	43	0	0
T183	0	50	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	2596	0	0
T1	107082	6	0	0
T2	5738	0	0	0
T3	7982	0	0	0
T4	3190	0	0	0
T12	9283	0	0	0
T13	25297	0	0	0
T14	9853	0	0	0
T15	1716	0	0	0
T16	5602	0	0	0
T17	10574	0	0	0
T51	0	16	0	0
T52	0	10	0	0
T53	0	78	0	0
T74	0	26	0	0
T95	0	32	0	0
T100	0	57	0	0
T119	0	66	0	0
T179	0	24	0	0
T185	0	87	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1988	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	12	0	0
T53	0	37	0	0
T57	3022	0	0	0
T75	0	61	0	0
T82	7373	0	0	0
T95	30596	29	0	0
T100	0	78	0	0
T119	0	17	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	24	0	0
T181	0	15	0	0
T182	0	46	0	0
T183	0	31	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	2007	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	9	0	0
T53	0	18	0	0
T57	3022	0	0	0
T75	0	84	0	0
T82	7373	0	0	0
T95	30596	38	0	0
T100	0	66	0	0
T119	0	29	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	39	0	0
T181	0	11	0	0
T182	0	39	0	0
T183	0	61	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1847	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	13	0	0
T53	0	20	0	0
T57	3022	0	0	0
T75	0	68	0	0
T82	7373	0	0	0
T95	30596	26	0	0
T100	0	46	0	0
T119	0	11	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	30	0	0
T181	0	9	0	0
T182	0	22	0	0
T183	0	77	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1916	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	25	0	0
T53	0	47	0	0
T57	3022	0	0	0
T75	0	68	0	0
T82	7373	0	0	0
T95	30596	23	0	0
T100	0	104	0	0
T119	0	29	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	31	0	0
T181	0	6	0	0
T182	0	24	0	0
T183	0	62	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1917	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	28	0	0
T53	0	35	0	0
T57	3022	0	0	0
T75	0	52	0	0
T82	7373	0	0	0
T95	30596	16	0	0
T100	0	88	0	0
T119	0	18	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	31	0	0
T181	0	6	0	0
T182	0	24	0	0
T183	0	34	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	2028	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	11	0	0
T53	0	40	0	0
T57	3022	0	0	0
T75	0	58	0	0
T82	7373	0	0	0
T95	30596	13	0	0
T100	0	67	0	0
T119	0	52	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	26	0	0
T181	0	2	0	0
T182	0	37	0	0
T183	0	75	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1895	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	20	0	0
T53	0	23	0	0
T57	3022	0	0	0
T75	0	58	0	0
T82	7373	0	0	0
T95	30596	33	0	0
T100	0	87	0	0
T119	0	22	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	29	0	0
T181	0	7	0	0
T182	0	23	0	0
T183	0	45	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1927	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	21	0	0
T53	0	33	0	0
T57	3022	0	0	0
T75	0	51	0	0
T82	7373	0	0	0
T95	30596	16	0	0
T100	0	58	0	0
T119	0	27	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	28	0	0
T181	0	13	0	0
T182	0	31	0	0
T183	0	67	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1935	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	10	0	0
T53	0	55	0	0
T57	3022	0	0	0
T75	0	50	0	0
T82	7373	0	0	0
T95	30596	33	0	0
T100	0	83	0	0
T119	0	6	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	38	0	0
T181	0	1	0	0
T182	0	30	0	0
T183	0	49	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1972	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	14	0	0
T53	0	34	0	0
T57	3022	0	0	0
T75	0	76	0	0
T82	7373	0	0	0
T95	30596	31	0	0
T100	0	53	0	0
T119	0	25	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	14	0	0
T181	0	16	0	0
T182	0	38	0	0
T183	0	31	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1833	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	16	0	0
T53	0	38	0	0
T57	3022	0	0	0
T75	0	50	0	0
T82	7373	0	0	0
T95	30596	39	0	0
T100	0	58	0	0
T119	0	48	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	48	0	0
T181	0	1	0	0
T182	0	44	0	0
T183	0	52	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1905	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	17	0	0
T53	0	19	0	0
T57	3022	0	0	0
T75	0	69	0	0
T82	7373	0	0	0
T95	30596	14	0	0
T100	0	73	0	0
T119	0	17	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	34	0	0
T181	0	12	0	0
T182	0	15	0	0
T183	0	59	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1863	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	11	0	0
T53	0	10	0	0
T57	3022	0	0	0
T75	0	49	0	0
T82	7373	0	0	0
T95	30596	26	0	0
T100	0	68	0	0
T119	0	13	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	41	0	0
T181	0	18	0	0
T182	0	25	0	0
T183	0	92	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	2023	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	14	0	0
T53	0	18	0	0
T57	3022	0	0	0
T75	0	69	0	0
T82	7373	0	0	0
T95	30596	31	0	0
T100	0	64	0	0
T119	0	41	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	24	0	0
T181	0	6	0	0
T182	0	32	0	0
T183	0	77	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1967	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	8	0	0
T53	0	46	0	0
T57	3022	0	0	0
T75	0	67	0	0
T82	7373	0	0	0
T95	30596	58	0	0
T100	0	69	0	0
T119	0	33	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	20	0	0
T181	0	5	0	0
T182	0	33	0	0
T183	0	65	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1887	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	15	0	0
T53	0	20	0	0
T57	3022	0	0	0
T75	0	72	0	0
T82	7373	0	0	0
T95	30596	45	0	0
T100	0	84	0	0
T119	0	21	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	32	0	0
T181	0	12	0	0
T182	0	8	0	0
T183	0	65	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1990	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	9	0	0
T53	0	25	0	0
T57	3022	0	0	0
T75	0	65	0	0
T82	7373	0	0	0
T95	30596	34	0	0
T100	0	95	0	0
T119	0	17	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	33	0	0
T181	0	22	0	0
T182	0	49	0	0
T183	0	79	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1974	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	18	0	0
T53	0	39	0	0
T57	3022	0	0	0
T75	0	53	0	0
T82	7373	0	0	0
T95	30596	34	0	0
T100	0	103	0	0
T119	0	46	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	57	0	0
T181	0	9	0	0
T182	0	22	0	0
T183	0	67	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	2052	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	12	0	0
T53	0	48	0	0
T57	3022	0	0	0
T75	0	66	0	0
T82	7373	0	0	0
T95	30596	20	0	0
T100	0	76	0	0
T119	0	43	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	22	0	0
T181	0	9	0	0
T182	0	41	0	0
T183	0	64	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1963	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	8	0	0
T53	0	17	0	0
T57	3022	0	0	0
T75	0	61	0	0
T82	7373	0	0	0
T95	30596	19	0	0
T100	0	41	0	0
T119	0	16	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	38	0	0
T181	0	13	0	0
T182	0	22	0	0
T183	0	70	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1939	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	17	0	0
T53	0	19	0	0
T57	3022	0	0	0
T75	0	72	0	0
T82	7373	0	0	0
T95	30596	31	0	0
T100	0	69	0	0
T119	0	23	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	36	0	0
T181	0	11	0	0
T182	0	36	0	0
T183	0	76	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26581190	1926	0	0
T40	9650	0	0	0
T48	19076	0	0	0
T51	0	23	0	0
T53	0	50	0	0
T57	3022	0	0	0
T75	0	77	0	0
T82	7373	0	0	0
T95	30596	34	0	0
T100	0	60	0	0
T119	0	28	0	0
T121	5720	0	0	0
T122	4009	0	0	0
T123	12279	0	0	0
T124	1245	0	0	0
T125	12614	0	0	0
T180	0	45	0	0
T181	0	18	0	0
T182	0	15	0	0
T183	0	48	0	0