Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3227734	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

573079

1

T1

273

T2

179

T3

222

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3406651	1			T1	1943		T2	590		T3	489
values[0x0]	196015	1			T1	118		T2	42		T3	63
values[0x1]	198147	1			T1	147		T2	56		T3	58

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2208197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1592616

1

T1

905

T2

325

T3

295

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13352	1			T1	17		T2	2		T4	4
valid_sources[0x01]	12041	1			T1	35		T2	4		T3	3
valid_sources[0x02]	30108	1			T2	7		T3	2		T4	4
valid_sources[0x03]	17100	1			T1	3		T2	3		T3	5
valid_sources[0x04]	12247	1			T1	24		T2	1		T3	2
valid_sources[0x05]	12749	1			T1	1		T2	4		T3	2
valid_sources[0x06]	12568	1			T2	5		T4	7		T15	13
valid_sources[0x07]	11778	1			T2	1		T3	1		T4	9
valid_sources[0x08]	12015	1			T2	2		T3	1		T4	7
valid_sources[0x09]	12186	1			T4	6		T15	12		T17	4
valid_sources[0x0a]	13064	1			T1	11		T2	4		T3	1
valid_sources[0x0b]	11403	1			T1	7		T2	2		T3	8
valid_sources[0x0c]	13664	1			T2	1		T4	4		T15	21
valid_sources[0x0d]	12075	1			T3	7		T4	6		T15	7
valid_sources[0x0e]	11556	1			T2	3		T3	1		T4	6
valid_sources[0x0f]	12252	1			T2	1		T3	1		T4	9
valid_sources[0x10]	13240	1			T2	2		T3	5		T4	5
valid_sources[0x11]	12016	1			T2	3		T4	12		T15	14
valid_sources[0x12]	12580	1			T2	3		T3	6		T4	4
valid_sources[0x13]	11785	1			T2	1		T3	7		T4	7
valid_sources[0x14]	12588	1			T2	2		T3	5		T4	6
valid_sources[0x15]	12053	1			T1	18		T2	6		T4	6
valid_sources[0x16]	20230	1			T2	5		T3	4		T4	8
valid_sources[0x17]	17158	1			T2	4		T3	3		T4	2
valid_sources[0x18]	11970	1			T1	34		T2	2		T3	1
valid_sources[0x19]	14001	1			T2	3		T3	1		T4	5
valid_sources[0x1a]	12457	1			T1	84		T2	2		T3	1
valid_sources[0x1b]	11515	1			T2	2		T3	6		T4	7
valid_sources[0x1c]	19485	1			T1	52		T3	2		T4	9
valid_sources[0x1d]	12726	1			T2	2		T3	2		T4	7
valid_sources[0x1e]	12209	1			T1	28		T2	2		T3	1
valid_sources[0x1f]	12708	1			T2	2		T3	2		T4	10
valid_sources[0x20]	13357	1			T1	24		T2	1		T3	2
valid_sources[0x21]	12046	1			T2	7		T3	2		T4	13
valid_sources[0x22]	11886	1			T2	3		T3	4		T4	11
valid_sources[0x23]	18884	1			T2	2		T3	1		T4	13
valid_sources[0x24]	12983	1			T3	1		T4	5		T15	8
valid_sources[0x25]	13233	1			T1	13		T2	3		T4	9
valid_sources[0x26]	14622	1			T1	26		T2	2		T3	1
valid_sources[0x27]	12559	1			T1	56		T2	2		T3	1
valid_sources[0x28]	13698	1			T2	1		T4	8		T15	16
valid_sources[0x29]	11890	1			T2	3		T3	2		T4	7
valid_sources[0x2a]	11795	1			T3	3		T4	6		T15	12
valid_sources[0x2b]	21435	1			T1	45		T2	4		T3	1
valid_sources[0x2c]	12257	1			T2	6		T3	3		T4	9
valid_sources[0x2d]	13317	1			T1	50		T2	2		T3	1
valid_sources[0x2e]	12870	1			T2	3		T3	6		T4	3
valid_sources[0x2f]	11892	1			T1	48		T2	6		T4	17
valid_sources[0x30]	14047	1			T2	2		T3	3		T4	9
valid_sources[0x31]	12993	1			T2	2		T3	1		T4	9
valid_sources[0x32]	13098	1			T1	40		T2	3		T3	3
valid_sources[0x33]	12122	1			T1	26		T2	3		T3	2
valid_sources[0x34]	12614	1			T2	3		T3	3		T4	8
valid_sources[0x35]	20050	1			T2	1		T3	4		T4	6
valid_sources[0x36]	11955	1			T2	3		T3	2		T4	8
valid_sources[0x37]	11575	1			T1	24		T2	2		T3	1
valid_sources[0x38]	14684	1			T2	2		T3	1		T4	12
valid_sources[0x39]	12705	1			T2	2		T3	2		T4	7
valid_sources[0x3a]	11548	1			T2	1		T3	4		T4	9
valid_sources[0x3b]	29868	1			T1	4		T2	1		T3	1
valid_sources[0x3c]	12350	1			T2	8		T3	1		T4	6
valid_sources[0x3d]	11461	1			T2	2		T3	4		T4	5
valid_sources[0x3e]	12216	1			T2	4		T3	3		T4	3
valid_sources[0x3f]	11284	1			T2	1		T3	3		T4	6
valid_sources[0x40]	19417	1			T2	3		T3	1		T4	9
valid_sources[0x41]	11923	1			T1	12		T2	4		T4	7
valid_sources[0x42]	13448	1			T2	1		T4	7		T15	8
valid_sources[0x43]	14576	1			T2	1		T4	7		T15	8
valid_sources[0x44]	24260	1			T2	7		T3	2		T4	10
valid_sources[0x45]	29253	1			T2	1		T3	2		T4	4
valid_sources[0x46]	15560	1			T2	1		T3	2		T4	8
valid_sources[0x47]	11538	1			T2	3		T3	2		T4	7
valid_sources[0x48]	36274	1			T1	11		T2	2		T3	4
valid_sources[0x49]	12723	1			T1	88		T2	4		T3	3
valid_sources[0x4a]	12000	1			T2	2		T3	2		T4	6
valid_sources[0x4b]	12423	1			T2	1		T3	2		T4	3
valid_sources[0x4c]	15521	1			T2	2		T4	4		T15	18
valid_sources[0x4d]	11628	1			T1	17		T4	3		T15	6
valid_sources[0x4e]	19855	1			T2	2		T3	3		T4	9
valid_sources[0x4f]	21038	1			T2	3		T3	2		T4	8
valid_sources[0x50]	11908	1			T2	3		T3	1		T4	3
valid_sources[0x51]	37473	1			T3	2		T4	8		T15	11
valid_sources[0x52]	12296	1			T2	6		T3	2		T4	5
valid_sources[0x53]	11889	1			T2	1		T3	1		T4	8
valid_sources[0x54]	22624	1			T1	1		T2	6		T3	4
valid_sources[0x55]	13285	1			T2	4		T3	4		T4	11
valid_sources[0x56]	12678	1			T2	3		T4	12		T15	6
valid_sources[0x57]	12106	1			T2	5		T3	8		T4	8
valid_sources[0x58]	15090	1			T2	2		T3	3		T4	12
valid_sources[0x59]	15035	1			T2	1		T3	2		T4	7
valid_sources[0x5a]	12447	1			T3	1		T4	7		T15	12
valid_sources[0x5b]	18057	1			T2	3		T3	5		T4	6
valid_sources[0x5c]	11616	1			T2	4		T3	1		T4	8
valid_sources[0x5d]	20321	1			T2	4		T4	6		T15	15
valid_sources[0x5e]	12757	1			T2	3		T3	4		T4	13
valid_sources[0x5f]	12067	1			T2	2		T3	2		T4	10
valid_sources[0x60]	11175	1			T2	2		T3	3		T4	5
valid_sources[0x61]	12437	1			T2	4		T4	3		T15	14
valid_sources[0x62]	15712	1			T1	5		T2	2		T4	5
valid_sources[0x63]	13018	1			T1	14		T2	1		T3	3
valid_sources[0x64]	17081	1			T3	1		T4	4		T15	13
valid_sources[0x65]	11457	1			T2	1		T3	1		T4	7
valid_sources[0x66]	13760	1			T1	58		T2	3		T3	2
valid_sources[0x67]	11381	1			T2	3		T3	3		T4	2
valid_sources[0x68]	11372	1			T2	6		T3	2		T4	13
valid_sources[0x69]	13621	1			T1	3		T2	7		T3	1
valid_sources[0x6a]	11555	1			T2	4		T3	1		T4	6
valid_sources[0x6b]	20380	1			T1	16		T2	1		T3	4
valid_sources[0x6c]	11947	1			T2	4		T3	2		T4	6
valid_sources[0x6d]	14858	1			T2	10		T3	2		T4	7
valid_sources[0x6e]	12227	1			T1	2		T3	7		T4	7
valid_sources[0x6f]	14681	1			T2	3		T3	2		T4	12
valid_sources[0x70]	12589	1			T2	1		T4	15		T15	10
valid_sources[0x71]	14689	1			T2	2		T3	3		T4	5
valid_sources[0x72]	12354	1			T2	3		T3	5		T4	5
valid_sources[0x73]	11742	1			T1	13		T2	2		T3	3
valid_sources[0x74]	54304	1			T2	3		T3	6		T4	5
valid_sources[0x75]	12180	1			T2	2		T3	2		T4	8
valid_sources[0x76]	11728	1			T2	1		T3	1		T4	7
valid_sources[0x77]	15023	1			T2	4		T3	2		T4	13
valid_sources[0x78]	14099	1			T1	3		T2	3		T4	14
valid_sources[0x79]	14833	1			T2	1		T4	4		T15	14
valid_sources[0x7a]	12485	1			T1	7		T2	6		T3	2
valid_sources[0x7b]	12106	1			T2	7		T3	1		T4	4
valid_sources[0x7c]	13015	1			T1	4		T2	3		T3	2
valid_sources[0x7d]	11904	1			T2	3		T3	6		T4	6
valid_sources[0x7e]	13710	1			T2	6		T3	6		T4	6
valid_sources[0x7f]	13159	1			T2	3		T3	5		T4	3
valid_sources[0x80]	11719	1			T2	1		T4	8		T15	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

304932

1

T1

92

T2

150

T3

186

values[0x0]

all_enables

biggest_size

141049

1

T1

86

T2

14

T3

23

values[0x1]

all_enables

biggest_size

127098

1

T1

95

T2

15

T3

13